From fd1d3d80e00a92d2c1237c43221ce4f38be9692d Mon Sep 17 00:00:00 2001 From: Silaghi Date: Tue, 26 May 2026 02:51:13 +0300 Subject: [PATCH] Revert "Bug 1929128, Bug 2040802 : Use SIMD for SkipUntilBitInTable r=jandem" for causing spidermonkey failures at wasm\simd\baseline This reverts commit f297ecf8d64fd00ac7b62fbbfcf4df74e3c26932. Revert "Bug 2040802: Rename ENABLE_WASM_SIMD to ENABLE_JIT_SIMD r=yury" This reverts commit f9b0d3c303188b764cb55a73234f92eea1d64d4f. --- js/moz.configure | 75 +++++----- js/public/Initialization.h | 2 +- js/src/builtin/TestingFunctions.cpp | 6 +- .../irregexp/RegExpNativeMacroAssembler.cpp | 134 +----------------- js/src/irregexp/RegExpNativeMacroAssembler.h | 3 - js/src/jit-test/tests/wasm/simd/disabled.js | 3 +- js/src/jit/CodeGenerator.cpp | 10 +- js/src/jit/JitContext.cpp | 2 +- js/src/jit/LIR.cpp | 2 +- js/src/jit/LIR.h | 2 +- js/src/jit/Lowering.cpp | 8 +- js/src/jit/MIR-wasm.cpp | 14 +- js/src/jit/MIR-wasm.h | 22 +-- js/src/jit/MacroAssembler.h | 2 +- js/src/jit/ShuffleAnalysis.cpp | 4 +- js/src/jit/ShuffleAnalysis.h | 2 +- js/src/jit/arm/Architecture-arm.cpp | 6 +- js/src/jit/arm/Lowering-arm.cpp | 2 +- js/src/jit/arm/MacroAssembler-arm.cpp | 6 +- js/src/jit/arm/Trampoline-arm.cpp | 2 +- js/src/jit/arm64/Assembler-arm64.cpp | 2 +- js/src/jit/arm64/Assembler-arm64.h | 2 +- js/src/jit/arm64/CodeGenerator-arm64.cpp | 38 ++--- js/src/jit/arm64/Lowering-arm64.cpp | 24 ++-- js/src/jit/arm64/Lowering-arm64.h | 2 +- js/src/jit/arm64/MacroAssembler-arm64.cpp | 2 +- js/src/jit/loong64/Architecture-loong64.cpp | 6 +- js/src/jit/loong64/Lowering-loong64.cpp | 2 +- js/src/jit/loong64/MacroAssembler-loong64.cpp | 6 +- .../jit/mips-shared/Lowering-mips-shared.cpp | 2 +- js/src/jit/mips64/Architecture-mips64.cpp | 4 +- js/src/jit/mips64/MacroAssembler-mips64.cpp | 6 +- js/src/jit/riscv64/Architecture-riscv64.cpp | 4 +- js/src/jit/riscv64/Architecture-riscv64.h | 2 +- js/src/jit/riscv64/Lowering-riscv64.cpp | 2 +- js/src/jit/riscv64/MacroAssembler-riscv64.cpp | 6 +- js/src/jit/riscv64/Register-riscv64.h | 2 +- js/src/jit/shared/CodeGenerator-shared.cpp | 2 +- js/src/jit/shared/Lowering-shared-inl.h | 4 +- js/src/jit/shared/Lowering-shared.h | 2 +- js/src/jit/x64/Lowering-x64.cpp | 2 +- js/src/jit/x64/Trampoline-x64.cpp | 2 +- .../x86-shared/Architecture-x86-shared.cpp | 2 +- .../jit/x86-shared/Assembler-x86-shared.cpp | 2 +- .../x86-shared/CodeGenerator-x86-shared.cpp | 42 +++--- js/src/jit/x86-shared/Lowering-x86-shared.cpp | 28 ++-- js/src/jit/x86-shared/Lowering-x86-shared.h | 2 +- .../x86-shared/MacroAssembler-x86-shared.cpp | 2 +- js/src/jit/x86/Lowering-x86.cpp | 2 +- js/src/jit/x86/Trampoline-x86.cpp | 2 +- js/src/shell/js.cpp | 2 +- js/src/vm/Initialization.cpp | 2 +- js/src/wasm/WasmBCClass.h | 30 ++-- js/src/wasm/WasmBCCodegen-inl.h | 6 +- js/src/wasm/WasmBCFrame.cpp | 10 +- js/src/wasm/WasmBCFrame.h | 14 +- js/src/wasm/WasmBCMemory.cpp | 20 +-- js/src/wasm/WasmBCRegDefs-inl.h | 4 +- js/src/wasm/WasmBCRegDefs.h | 30 ++-- js/src/wasm/WasmBCRegMgmt-inl.h | 20 +-- js/src/wasm/WasmBCStk.h | 30 ++-- js/src/wasm/WasmBCStkMgmt-inl.h | 28 ++-- js/src/wasm/WasmBaselineCompile.cpp | 52 +++---- js/src/wasm/WasmBinary.h | 8 +- js/src/wasm/WasmDebugFrame.cpp | 2 +- js/src/wasm/WasmDebugFrame.h | 4 +- js/src/wasm/WasmFeatures.h | 2 +- js/src/wasm/WasmInitExpr.cpp | 4 +- js/src/wasm/WasmIonCompile.cpp | 40 +++--- js/src/wasm/WasmOpIter.cpp | 2 +- js/src/wasm/WasmOpIter.h | 10 +- js/src/wasm/WasmStubs.cpp | 30 ++-- js/src/wasm/WasmStubs.h | 2 +- js/src/wasm/WasmValType.cpp | 2 +- js/src/wasm/WasmValType.h | 10 +- js/src/wasm/WasmValidate.cpp | 4 +- js/xpconnect/src/nsXPConnect.cpp | 2 +- modules/libpref/init/StaticPrefList.yaml | 2 +- 78 files changed, 381 insertions(+), 504 deletions(-) diff --git a/js/moz.configure b/js/moz.configure index d29f3136fbbd..f6a6b3d36b61 100644 --- a/js/moz.configure +++ b/js/moz.configure @@ -812,12 +812,12 @@ def enable_shared_memory(value): set_config("ENABLE_SHARED_MEMORY", enable_shared_memory) set_define("ENABLE_SHARED_MEMORY", enable_shared_memory) -# Support for JIT SIMD +# Support for WebAssembly SIMD # ===================================================== @depends("--enable-jit", "--enable-simulator", target) -def default_jit_simd(jit_enabled, simulator, target): +def default_wasm_simd(jit_enabled, simulator, target): if not jit_enabled: return @@ -829,36 +829,37 @@ def default_jit_simd(jit_enabled, simulator, target): option( - "--enable-jit-simd", - default=default_jit_simd, - help="{Enable|Disable} JIT SIMD", + "--enable-wasm-simd", + default=default_wasm_simd, + help="{Enable|Disable} WebAssembly SIMD", ) @depends( - "--enable-jit-simd", + "--enable-wasm-simd", "--enable-jit", "--enable-simulator", target, + "--wasm-no-experimental", ) -def jit_simd(value, jit_enabled, simulator, target): - if not value: +def wasm_simd(value, jit_enabled, simulator, target, no_experimental): + if no_experimental or not value: return if not jit_enabled: - die("--enable-jit-simd requires --enable-jit") + die("--enable-wasm-simd requires --enable-jit") if simulator and (simulator[0] != "arm64"): - die("--enable-jit-simd is not supported for simulators, except arm64") + die("--enable-wasm-simd is not supported for simulators, except arm64") if target.cpu in ("x86_64", "x86", "aarch64"): return True - die("--enable-jit-simd only possible when targeting the x86_64/x86/arm64 jits") + die("--enable-wasm-simd only possible when targeting the x86_64/x86/arm64 jits") -set_config("ENABLE_JIT_SIMD", jit_simd) -set_define("ENABLE_JIT_SIMD", jit_simd) +set_config("ENABLE_WASM_SIMD", wasm_simd) +set_define("ENABLE_WASM_SIMD", wasm_simd) # Whether to check for field changes in WebAssembly serialization # @@ -895,12 +896,15 @@ set_define( ) # Support for Intel AVX instruction. +# +# AVX is exclusively used in WebAssembly SIMD instructions at the moment: +# set direct dependency on "--enable-wasm-simd". # ===================================================== -@depends("--enable-jit-simd", "--enable-simulator", target) -def default_jit_avx(jit_simd_enabled, simulator, target): - if not jit_simd_enabled: +@depends("--enable-wasm-simd", "--enable-simulator", target) +def default_wasm_avx(wasm_simd_enabled, simulator, target): + if not wasm_simd_enabled: return if simulator: @@ -911,44 +915,45 @@ def default_jit_avx(jit_simd_enabled, simulator, target): option( - "--enable-jit-avx", - default=default_jit_avx, - help="{Enable|Disable} AVX support for JIT SIMD", + "--enable-wasm-avx", + default=default_wasm_avx, + help="{Enable|Disable} AVX support for WebAssembly SIMD", ) @depends( - "--enable-jit-avx", - "--enable-jit-simd", + "--enable-wasm-avx", + "--enable-wasm-simd", "--enable-simulator", target, + "--wasm-no-experimental", ) -def jit_avx(value, jit_simd_enabled, simulator, target): - if not value: +def wasm_avx(value, wasm_simd_enabled, simulator, target, no_experimental): + if no_experimental or not value: return - if not jit_simd_enabled: - die("--enable-jit-avx requires --enable-jit-simd") + if not wasm_simd_enabled: + die("--enable-wasm-avx requires --enable-wasm-simd") if simulator: - die("--enable-jit-avx is not supported for simulators") + die("--enable-wasm-avx is not supported for simulators") if target.cpu in ("x86_64", "x86"): return True - die("--enable-jit-avx only possible when targeting the x86_64/x86 jits") + die("--enable-wasm-avx only possible when targeting the x86_64/x86 jits") -set_config("ENABLE_JIT_AVX", jit_avx) -set_define("ENABLE_JIT_AVX", jit_avx) +set_config("ENABLE_WASM_AVX", wasm_avx) +set_define("ENABLE_WASM_AVX", wasm_avx) # Support for WebAssembly relaxed SIMD # ===================================================== -@depends("--enable-jit-simd") -def default_wasm_relaxed_simd(jit_simd): - if jit_simd: +@depends("--enable-wasm-simd") +def default_wasm_relaxed_simd(wasm_simd): + if wasm_simd: return True @@ -959,12 +964,12 @@ option( ) -@depends("--enable-wasm-relaxed-simd", "--enable-jit-simd") -def wasm_relaxed_simd(value, jit_simd): +@depends("--enable-wasm-relaxed-simd", "--enable-wasm-simd") +def wasm_relaxed_simd(value, wasm_simd): if not value: return - if not jit_simd: + if not wasm_simd: die("relaxed SIMD requires SIMD") return True diff --git a/js/public/Initialization.h b/js/public/Initialization.h index 26578b6efd93..8467e5850b8b 100644 --- a/js/public/Initialization.h +++ b/js/public/Initialization.h @@ -196,7 +196,7 @@ extern JS_PUBLIC_API void JS_ShutDown(void); */ extern JS_PUBLIC_API void JS_FrontendOnlyShutDown(void); -#if defined(ENABLE_JIT_SIMD) && \ +#if defined(ENABLE_WASM_SIMD) && \ (defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)) namespace JS { // Enable support for AVX instructions in the JIT/Wasm backend on x86/x64 diff --git a/js/src/builtin/TestingFunctions.cpp b/js/src/builtin/TestingFunctions.cpp index 93d5fa5562cc..00806fe14fd3 100644 --- a/js/src/builtin/TestingFunctions.cpp +++ b/js/src/builtin/TestingFunctions.cpp @@ -1074,7 +1074,7 @@ static bool GetWasmSupportedFeatures(JSContext* cx, unsigned argc, Value* vp) { JS_FOR_WASM_FEATURES(WASM_FEATURE); #undef WASM_FEATURE -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD value.setBoolean(true); #else value.setBoolean(false); @@ -1239,7 +1239,7 @@ static bool WasmIonDisabledByFeatures(JSContext* cx, unsigned argc, Value* vp) { return true; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # ifdef DEBUG static char lastAnalysisResult[1024]; @@ -10861,7 +10861,7 @@ JS_FOR_WASM_FEATURES(WASM_FEATURE) " Returns a boolean indicating whether WebAssembly SIMD proposal is\n" " supported by the current device."), -#if defined(ENABLE_JIT_SIMD) && defined(DEBUG) +#if defined(ENABLE_WASM_SIMD) && defined(DEBUG) JS_FN_HELP("wasmSimdAnalysis", WasmSimdAnalysis, 1, 0, "wasmSimdAnalysis(...)", " Unstable API for white-box testing.\n"), diff --git a/js/src/irregexp/RegExpNativeMacroAssembler.cpp b/js/src/irregexp/RegExpNativeMacroAssembler.cpp index 2961c73b98d1..ae351226797b 100644 --- a/js/src/irregexp/RegExpNativeMacroAssembler.cpp +++ b/js/src/irregexp/RegExpNativeMacroAssembler.cpp @@ -27,13 +27,10 @@ namespace regexp { using js::MatchPairs; using js::jit::AbsoluteAddress; using js::jit::Address; -using js::jit::AllocatableFloatRegisterSet; using js::jit::AllocatableGeneralRegisterSet; using js::jit::Assembler; using js::jit::BaseIndex; using js::jit::CodeLocationLabel; -using js::jit::FloatRegister; -using js::jit::FloatRegisterSet; using js::jit::GeneralRegisterBackwardIterator; using js::jit::GeneralRegisterForwardIterator; using js::jit::GeneralRegisterSet; @@ -45,7 +42,6 @@ using js::jit::Linker; using js::jit::LiveGeneralRegisterSet; using js::jit::Register; using js::jit::Registers; -using js::jit::SimdConstant; using js::jit::StackMacroAssembler; SMRegExpMacroAssembler::SMRegExpMacroAssembler(JSContext* cx, @@ -382,17 +378,8 @@ void SMRegExpMacroAssembler::SkipUntilBitInTable( // owned by the RegExpShared. PseudoHandle rawTable = table->takeOwnership(isolate()); - bool useSimd = SkipUntilBitInTableUseSimd(advance_by); - if (useSimd) { - PseudoHandle rawNibbleTable = - nibble_table->takeOwnership(isolate()); - - MOZ_ASSERT(advance_by == 1); - EmitSkipUntilBitInTableSimd(cp_offset, rawNibbleTable.get(), on_match); - AddTable(std::move(rawNibbleTable)); - // Fall through and handle the remaining characters using - // the scalar version. - } + // TODO: SIMD support (bug 1929128). + MOZ_ASSERT(!SkipUntilBitInTableUseSimd(advance_by)); // Scalar version. Register tableReg = temp0_; @@ -419,124 +406,11 @@ void SMRegExpMacroAssembler::SkipUntilBitInTable( AddTable(std::move(rawTable)); } -void SMRegExpMacroAssembler::EmitSkipUntilBitInTableSimd( - int cp_offset, ByteArrayData* nibble_table, Label* on_match) { -#ifdef ENABLE_JIT_SIMD - // The nibble table is only large enough to cover latin-1. - MOZ_ASSERT(mode_ == LATIN1); - - static constexpr int32_t VectorSize = 16; - const int32_t CharsPerVector = VectorSize / char_size(); - - // Hoist the bounds check. - // We fall back to the scalar version once there are less than CharsPerVector - // chars left in the input. We subtract 1 because CheckPosition already - // assumes we're reading 1 char. - Label scalarFallback; - static const int32_t ExtraCharsPerVector = CharsPerVector - 1; - CheckPosition(cp_offset + ExtraCharsPerVector, &scalarFallback); - - // Allocate SIMD scratch registers from the volatile set. - AllocatableFloatRegisterSet floatRegs(FloatRegisterSet::Volatile()); - FloatRegister nibbleTable = floatRegs.takeAny().asSimd128(); - FloatRegister nibbleMask = floatRegs.takeAny().asSimd128(); - FloatRegister hiLookup = floatRegs.takeAny().asSimd128(); - FloatRegister inputVec = floatRegs.takeAny().asSimd128(); - FloatRegister loNibbles = floatRegs.takeAny().asSimd128(); - FloatRegister bitmask = floatRegs.takeAny().asSimd128(); - - // Hoist constants outside the loop. - // nibbleTable: 16-byte Boyer-Moore nibble table from regexp data. - masm_.movePtr(ImmPtr(nibble_table->data()), temp0_); - masm_.loadUnalignedSimd128(Address(temp0_, 0), nibbleTable); - // nibbleMask: 0x0f repeated 16 times. - masm_.loadConstantSimd128(SimdConstant::SplatX16(int8_t(0x0f)), nibbleMask); - // hiLookup: bit-position table {0x01,0x02,0x04,...,0x80} repeated twice. - masm_.loadConstantSimd128( - SimdConstant::SplatX2(int64_t(0x8040201008040201LL)), hiLookup); - - // We loop over the input, 16 bytes at a time. For each byte, we use the low - // nibble to index into the nibble table, then use the high nibble to index - // into the resulting byte. For example, 'b' (0x62) loads byte 2 from the - // table, then checks bit 6. See BoyerMooreLookahead::GetSkipTable. We - // continue until we find a matching character. Note that there are 256 - // latin-1 characters, but only 128 bits of table. We ignore the high bit of - // each character (hence the repetition in `hiLookup`), meaning that (for - // example) 'b' (0x62) and 'รข' (0xe2) share a bit. This isn't a correctness - // issue because the code following this SkipUntilBitInTable will check for a - // match separately. - - js::jit::Label simdLoop, advanceVector; - masm_.bind(&simdLoop); - - // Load the next 16 input bytes. - BaseIndex inputAddr(input_end_pointer_, current_position_, js::jit::TimesOne, - cp_offset); - masm_.loadUnalignedSimd128(inputAddr, inputVec); - - // loNibbles = inputVec & 0x0f - masm_.bitwiseAndSimd128(nibbleMask, inputVec, loNibbles); - - // hiNibbles = inputVec >> 4 - FloatRegister hiNibbles = inputVec; - masm_.unsignedRightShiftInt8x16(Imm32(4), inputVec, hiNibbles); - - // For each byte, load the correct row of the table. - // row = nibbleTable[loNibbles] - // bitmask = hiLookup[hiNibbles] - FloatRegister row = loNibbles; - masm_.swizzleInt8x16Relaxed(nibbleTable, loNibbles, row); - masm_.swizzleInt8x16Relaxed(hiLookup, hiNibbles, bitmask); - - // Check whether the corresponding bit is set. - // result = (row & bitmask)) == bitmask - FloatRegister result = loNibbles; - masm_.bitwiseAndSimd128(bitmask, row, result); - masm_.compareInt8x16(Assembler::Equal, result, bitmask, result); - - // Extract high bit of each byte into temp1 -# if defined(JS_CODEGEN_ARM64) - masm_.bitmaskInt8x16(result, temp1_, /*temp=*/bitmask); -# elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) - masm_.bitmaskInt8x16(result, temp1_); -# else -# error Unsupported SIMD architecture -# endif - - masm_.branchTest32(Assembler::Zero, temp1_, temp1_, &advanceVector); - - // Found a match in this 16-byte chunk. Locate the lowest set bit and - // advance current_position_ by that index, then jump to on_match. - masm_.ctz32(temp1_, temp0_, /*knownNotZero=*/true); - masm_.addPtr(temp0_, current_position_); - masm_.jump(LabelOrBacktrack(on_match)); - - masm_.bind(&advanceVector); - masm_.addPtr(Imm32(VectorSize), current_position_); - - CheckPosition(cp_offset + ExtraCharsPerVector, &scalarFallback); - masm_.jump(&simdLoop); - - masm_.bind(scalarFallback.inner()); -#else - MOZ_CRASH("SIMD not supported"); -#endif // ENABLE_JIT_SIMD -} - bool SMRegExpMacroAssembler::SkipUntilBitInTableUseSimd(int advance_by) { -#if defined(ENABLE_JIT_SIMD) -# if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) - // SSSE3 is required for pshufb (used to implement swizzleInt8x16). - if (!js::jit::Assembler::HasSSE3()) { - return false; - } -# endif // V8 found that using SIMD instead of the scalar version was only // faster when we are advancing by 1 byte per iteration. - return advance_by * char_size() == 1; -#else - return false; -#endif + bool simdEnabled = false; + return simdEnabled && advance_by * char_size() == 1; } void SMRegExpMacroAssembler::CheckNotBackReferenceImpl(int start_reg, diff --git a/js/src/irregexp/RegExpNativeMacroAssembler.h b/js/src/irregexp/RegExpNativeMacroAssembler.h index c27f002a7d13..8070c35d5cb6 100644 --- a/js/src/irregexp/RegExpNativeMacroAssembler.h +++ b/js/src/irregexp/RegExpNativeMacroAssembler.h @@ -149,9 +149,6 @@ class SMRegExpMacroAssembler final : public NativeRegExpMacroAssembler { void LoadCurrentCharacterUnchecked(int cp_offset, int characters); - void EmitSkipUntilBitInTableSimd(int cp_offset, ByteArrayData* nibble_table, - Label* on_match); - void JumpOrBacktrack(Label* to); // MacroAssembler methods that take a Label can be called with a diff --git a/js/src/jit-test/tests/wasm/simd/disabled.js b/js/src/jit-test/tests/wasm/simd/disabled.js index 6cd6fc75cced..feae41469711 100644 --- a/js/src/jit-test/tests/wasm/simd/disabled.js +++ b/js/src/jit-test/tests/wasm/simd/disabled.js @@ -5,7 +5,7 @@ // Non-opcode cases that should also be rejected, lest feature sniffing may // erroneously conclude that simd is available when it's not. The error message -// may differ depending on ENABLE_JIT_SIMD: if SIMD is compiled in we usually +// may differ depending on ENABLE_WASM_SIMD: if SIMD is compiled in we usually // get a sensible error about v128; if not, we get something generic. wasmFailValidateText(`(module (func (param v128)))`, @@ -25,3 +25,4 @@ wasmFailValidateText(`(module (global (import "m" "g") (mut v128)))`, wasmFailValidateText(`(module (global i32 (v128.const i32x4 0 0 0 0)))`, /(v128 not enabled)|(unrecognized opcode)/); + diff --git a/js/src/jit/CodeGenerator.cpp b/js/src/jit/CodeGenerator.cpp index 669a336b6d8e..b93e53987ac5 100644 --- a/js/src/jit/CodeGenerator.cpp +++ b/js/src/jit/CodeGenerator.cpp @@ -10818,7 +10818,7 @@ void CodeGenerator::visitWasmLoadSlot(LWasmLoadSlot* ins) { Address addr(container, ins->offset()); AnyRegister dst = ToAnyRegister(ins->output()); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (type == MIRType::Simd128) { MOZ_ASSERT(wideningOp == MWideningOp::None); FaultingCodeOffset fco = masm.loadUnalignedSimd128(addr, dst.fpu()); @@ -10837,7 +10837,7 @@ void CodeGenerator::visitWasmLoadElement(LWasmLoadElement* ins) { Register index = ToRegister(ins->index()); AnyRegister dst = ToAnyRegister(ins->output()); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (type == MIRType::Simd128) { MOZ_ASSERT(wideningOp == MWideningOp::None); FaultingCodeOffset fco; @@ -10862,7 +10862,7 @@ void CodeGenerator::visitWasmStoreSlot(LWasmStoreSlot* ins) { MOZ_RELEASE_ASSERT(narrowingOp == MNarrowingOp::None); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (type == MIRType::Simd128) { FaultingCodeOffset fco = masm.storeUnalignedSimd128(src.fpu(), addr); EmitSignalNullCheckTrapSite(masm, ins, fco, @@ -10887,7 +10887,7 @@ void CodeGenerator::visitWasmStoreStackResult(LWasmStoreStackResult* ins) { case MIRType::Double: masm.storeDouble(ToFloatRegister(value), addr); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: masm.storeUnalignedSimd128(ToFloatRegister(value), addr); break; @@ -10917,7 +10917,7 @@ void CodeGenerator::visitWasmStoreElement(LWasmStoreElement* ins) { MOZ_RELEASE_ASSERT(narrowingOp == MNarrowingOp::None); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (type == MIRType::Simd128) { Register temp = ToRegister(ins->temp0()); masm.lshiftPtr(Imm32(4), index, temp); diff --git a/js/src/jit/JitContext.cpp b/js/src/jit/JitContext.cpp index f83b20b84913..79b22d9f249f 100644 --- a/js/src/jit/JitContext.cpp +++ b/js/src/jit/JitContext.cpp @@ -153,7 +153,7 @@ void jit::ShutdownJit() { } bool jit::JitSupportsWasmSimd() { -#if defined(ENABLE_JIT_SIMD) +#if defined(ENABLE_WASM_SIMD) return js::jit::MacroAssembler::SupportsWasmSimd(); #else return false; diff --git a/js/src/jit/LIR.cpp b/js/src/jit/LIR.cpp index 2e1f7f6c541e..53425e390563 100644 --- a/js/src/jit/LIR.cpp +++ b/js/src/jit/LIR.cpp @@ -774,7 +774,7 @@ bool LMoveGroup::add(LAllocation from, LAllocation to, LDefinition::Type type) { // Check that SIMD moves are aligned according to ABI requirements. // clang-format off -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD // Alignment is not currently required for SIMD on x86/x64/arm64. See also // CodeGeneratorShared::CodeGeneratorShared and in general everywhere // SimdMemoryAignment is used. Likely, alignment requirements will return. diff --git a/js/src/jit/LIR.h b/js/src/jit/LIR.h index 27de888b1a06..3f4efeda7955 100644 --- a/js/src/jit/LIR.h +++ b/js/src/jit/LIR.h @@ -587,7 +587,7 @@ class LDefinition { static_assert(MAX_VIRTUAL_REGISTERS <= VREG_MASK); bits_ = (index << VREG_SHIFT) | (policy << POLICY_SHIFT) | (type << TYPE_SHIFT); -#ifndef ENABLE_JIT_SIMD +#ifndef ENABLE_WASM_SIMD MOZ_ASSERT(this->type() != SIMD128); #endif } diff --git a/js/src/jit/Lowering.cpp b/js/src/jit/Lowering.cpp index 5dabe7f8ef5f..9c1c4b0df491 100644 --- a/js/src/jit/Lowering.cpp +++ b/js/src/jit/Lowering.cpp @@ -1172,7 +1172,7 @@ void LIRGenerator::visitTest(MTest* test) { } } -#if defined(ENABLE_JIT_SIMD) && \ +#if defined(ENABLE_WASM_SIMD) && \ (defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) || \ defined(JS_CODEGEN_ARM64)) // Check if the operand for this test is an any_true/all_true SIMD operation. @@ -7182,7 +7182,7 @@ void LIRGenerator::visitWasmParameter(MWasmParameter* ins) { ); } else { MOZ_ASSERT(IsNumberType(ins->type()) || ins->type() == MIRType::WasmAnyRef -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD || ins->type() == MIRType::Simd128 #endif ); @@ -7206,7 +7206,7 @@ void LIRGenerator::visitWasmReturn(MWasmReturn* ins) { returnReg = useFixed(rval, ReturnFloat32Reg); } else if (rval->type() == MIRType::Double) { returnReg = useFixed(rval, ReturnDoubleReg); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD } else if (rval->type() == MIRType::Simd128) { returnReg = useFixed(rval, ReturnSimd128Reg); #endif @@ -8447,7 +8447,7 @@ void LIRGenerator::visitWasmFloatConstant(MWasmFloatConstant* ins) { case MIRType::Float32: define(new (alloc()) LFloat32(ins->toFloat32()), ins); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: define(new (alloc()) LSimd128(ins->toSimd128()), ins); break; diff --git a/js/src/jit/MIR-wasm.cpp b/js/src/jit/MIR-wasm.cpp index 4cbb711f46dc..b0d3b06d6a17 100644 --- a/js/src/jit/MIR-wasm.cpp +++ b/js/src/jit/MIR-wasm.cpp @@ -34,7 +34,7 @@ MInstruction* jit::NewWasmDefaultConstant(TempAllocator& alloc, case wasm::ValType::F64: return MWasmFloatConstant::NewDouble(alloc, 0.0); case wasm::ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD return MWasmFloatConstant::NewSimd128(alloc, SimdConstant::Zero()); #else MOZ_CRASH(); @@ -48,7 +48,7 @@ MInstruction* jit::NewWasmDefaultConstant(TempAllocator& alloc, } HashNumber MWasmFloatConstant::valueHash() const { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD return ConstantValueHash(type(), u.bits_[0] ^ u.bits_[1]); #else return ConstantValueHash(type(), u.bits_[0]); @@ -57,7 +57,7 @@ HashNumber MWasmFloatConstant::valueHash() const { bool MWasmFloatConstant::congruentTo(const MDefinition* ins) const { return ins->isWasmFloatConstant() && type() == ins->type() && -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD u.bits_[1] == ins->toWasmFloatConstant()->u.bits_[1] && #endif u.bits_[0] == ins->toWasmFloatConstant()->u.bits_[0]; @@ -428,7 +428,7 @@ bool MWasmLoadGlobalCell::congruentTo(const MDefinition* ins) const { return congruentIfOperandsEqual(other); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* MWasmTernarySimd128::foldsTo(TempAllocator& alloc) { if (simdOp() == wasm::SimdOp::V128Bitselect) { if (v2()->op() == MDefinition::Opcode::WasmFloatConstant) { @@ -771,7 +771,7 @@ MDefinition* MWasmReduceSimd128::foldsTo(TempAllocator& alloc) { # endif return this; } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD MDefinition* MWasmUnsignedToDouble::foldsTo(TempAllocator& alloc) { if (input()->isConstant()) { @@ -949,7 +949,7 @@ bool MWasmShuffleSimd128::congruentTo(const MDefinition* ins) const { congruentIfOperandsEqual(ins); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MWasmShuffleSimd128* jit::BuildWasmShuffleSimd128(TempAllocator& alloc, const int8_t* control, MDefinition* lhs, @@ -972,7 +972,7 @@ MWasmShuffleSimd128* jit::BuildWasmShuffleSimd128(TempAllocator& alloc, } return MWasmShuffleSimd128::New(alloc, lhs, rhs, s); } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD static MDefinition* FoldTrivialWasmTests(TempAllocator& alloc, wasm::RefType sourceType, diff --git a/js/src/jit/MIR-wasm.h b/js/src/jit/MIR-wasm.h index 00246c3ea1ef..1f00a81e07ed 100644 --- a/js/src/jit/MIR-wasm.h +++ b/js/src/jit/MIR-wasm.h @@ -77,7 +77,7 @@ class MWasmFloatConstant : public MNullaryInstruction { union { float f32_; double f64_; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD int8_t s128_[16]; uint64_t bits_[2]; #else @@ -87,7 +87,7 @@ class MWasmFloatConstant : public MNullaryInstruction { explicit MWasmFloatConstant(MIRType type) : MNullaryInstruction(classOpcode) { u.bits_[0] = 0; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD u.bits_[1] = 0; #endif setResultType(type); @@ -108,7 +108,7 @@ class MWasmFloatConstant : public MNullaryInstruction { return ret; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static MWasmFloatConstant* NewSimd128(TempAllocator& alloc, const SimdConstant& s) { auto* ret = new (alloc) MWasmFloatConstant(MIRType::Simd128); @@ -129,7 +129,7 @@ class MWasmFloatConstant : public MNullaryInstruction { MOZ_ASSERT(type() == MIRType::Float32); return u.f32_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD const SimdConstant toSimd128() const { MOZ_ASSERT(type() == MIRType::Simd128); return SimdConstant::CreateX16(u.s128_); @@ -145,7 +145,7 @@ class MWasmFloatConstant : public MNullaryInstruction { case MIRType::Double: SprintfLiteral(buf, "f64{%e}", u.f64_); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case MIRType::Simd128: SprintfLiteral(buf, "v128{[1]=%016llx:[0]=%016llx}", (unsigned long long int)u.bits_[1], @@ -2350,7 +2350,7 @@ class MWasmTernarySimd128 : public MTernaryInstruction, return congruentIfOperandsEqual(ins) && simdOp() == ins->toWasmTernarySimd128()->simdOp(); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* foldsTo(TempAllocator& alloc) override; // If the control mask of a bitselect allows the operation to be specialized @@ -2392,7 +2392,7 @@ class MWasmBinarySimd128 : public MBinaryInstruction, return congruentIfOperandsEqual(ins) && ins->toWasmBinarySimd128()->simdOp() == simdOp_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* foldsTo(TempAllocator& alloc) override; // Checks if pmaddubsw operation is supported. @@ -2490,7 +2490,7 @@ class MWasmScalarToSimd128 : public MUnaryInstruction, return congruentIfOperandsEqual(ins) && ins->toWasmScalarToSimd128()->simdOp() == simdOp_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* foldsTo(TempAllocator& alloc) override; #endif @@ -2521,7 +2521,7 @@ class MWasmReduceSimd128 : public MUnaryInstruction, public NoTypePolicy::Data { ins->toWasmReduceSimd128()->simdOp() == simdOp_ && ins->toWasmReduceSimd128()->imm() == imm_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* foldsTo(TempAllocator& alloc) override; #endif @@ -3576,12 +3576,12 @@ class MWasmMulI64WideHI64 : public MBinaryInstruction, #undef INSTRUCTION_HEADER -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MWasmShuffleSimd128* BuildWasmShuffleSimd128(TempAllocator& alloc, const int8_t* control, MDefinition* lhs, MDefinition* rhs); -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD } // namespace jit } // namespace js diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h index 7858530d3236..f8f0b0d09095 100644 --- a/js/src/jit/MacroAssembler.h +++ b/js/src/jit/MacroAssembler.h @@ -391,7 +391,7 @@ class MacroAssembler : public MacroAssemblerSpecific { void Push(RegisterOrSP reg); #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // `op` should be a shift operation. Return true if a variable-width shift // operation on this architecture should pre-mask the shift count, and if so, // return the mask in `*mask`. diff --git a/js/src/jit/ShuffleAnalysis.cpp b/js/src/jit/ShuffleAnalysis.cpp index 6ef19950e267..3fcf90acce86 100644 --- a/js/src/jit/ShuffleAnalysis.cpp +++ b/js/src/jit/ShuffleAnalysis.cpp @@ -17,7 +17,7 @@ using mozilla::Maybe; using mozilla::Nothing; using mozilla::Some; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Specialization analysis for SIMD operations. This is still x86-centric but // generalizes fairly easily to other architectures. @@ -843,4 +843,4 @@ SimdShuffle jit::AnalyzeSimdShuffle(SimdConstant control, MDefinition* lhs, # undef R } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD diff --git a/js/src/jit/ShuffleAnalysis.h b/js/src/jit/ShuffleAnalysis.h index 12f8152a4073..70383a80adc6 100644 --- a/js/src/jit/ShuffleAnalysis.h +++ b/js/src/jit/ShuffleAnalysis.h @@ -141,7 +141,7 @@ struct SimdShuffle { } }; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD SimdShuffle AnalyzeSimdShuffle(SimdConstant control, MDefinition* lhs, MDefinition* rhs); diff --git a/js/src/jit/arm/Architecture-arm.cpp b/js/src/jit/arm/Architecture-arm.cpp index 70192a26ccfd..82c37d2d2a55 100644 --- a/js/src/jit/arm/Architecture-arm.cpp +++ b/js/src/jit/arm/Architecture-arm.cpp @@ -413,7 +413,7 @@ FloatRegisters::Code FloatRegisters::FromName(const char* name) { } FloatRegisterSet VFPRegister::ReduceSetForPush(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -431,7 +431,7 @@ FloatRegisterSet VFPRegister::ReduceSetForPush(const FloatRegisterSet& s) { } uint32_t VFPRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -442,7 +442,7 @@ uint32_t VFPRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { return ret; } uint32_t VFPRegister::getRegisterDumpOffsetInBytes() { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/arm/Lowering-arm.cpp b/js/src/jit/arm/Lowering-arm.cpp index c4abdffcc123..c8aaff421e51 100644 --- a/js/src/jit/arm/Lowering-arm.cpp +++ b/js/src/jit/arm/Lowering-arm.cpp @@ -1138,7 +1138,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { MOZ_CRASH("binary SIMD NYI"); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { return false; diff --git a/js/src/jit/arm/MacroAssembler-arm.cpp b/js/src/jit/arm/MacroAssembler-arm.cpp index 62c719b553fd..410c20647e84 100644 --- a/js/src/jit/arm/MacroAssembler-arm.cpp +++ b/js/src/jit/arm/MacroAssembler-arm.cpp @@ -4210,7 +4210,7 @@ void MacroAssembler::PushRegsInMask(LiveRegisterSet set) { // It's possible that the logic is just fine as it is if the reduced set // maps SIMD pairs to plain doubles and transferMultipleByRuns() stores // and loads doubles. -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -4254,7 +4254,7 @@ void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, (void)diffG; // See above. -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -4281,7 +4281,7 @@ void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, const int32_t reservedF = diffF; // See above. -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/arm/Trampoline-arm.cpp b/js/src/jit/arm/Trampoline-arm.cpp index cdb705dd4b4c..659f1144ab92 100644 --- a/js/src/jit/arm/Trampoline-arm.cpp +++ b/js/src/jit/arm/Trampoline-arm.cpp @@ -335,7 +335,7 @@ void JitRuntime::generateInvalidator(MacroAssembler& masm, Label* bailoutTail) { } static void PushBailoutFrame(MacroAssembler& masm, Register spArg) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/arm64/Assembler-arm64.cpp b/js/src/jit/arm64/Assembler-arm64.cpp index ab1c94fddff8..f8296d72e32c 100644 --- a/js/src/jit/arm64/Assembler-arm64.cpp +++ b/js/src/jit/arm64/Assembler-arm64.cpp @@ -54,7 +54,7 @@ ABIArg ABIArgGenerator::next(MIRType type) { floatRegIndex_++; break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: if (floatRegIndex_ == NumFloatArgRegs) { stackOffset_ = AlignBytes(stackOffset_, SimdMemoryAlignment); diff --git a/js/src/jit/arm64/Assembler-arm64.h b/js/src/jit/arm64/Assembler-arm64.h index 3adc1ae888f2..e8ef2354a79e 100644 --- a/js/src/jit/arm64/Assembler-arm64.h +++ b/js/src/jit/arm64/Assembler-arm64.h @@ -54,7 +54,7 @@ struct ScratchFloat32Scope : public AutoFloatRegisterScope { : AutoFloatRegisterScope(masm, ScratchFloat32Reg_) {} }; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static constexpr FloatRegister ReturnSimd128Reg = {FloatRegisters::v0, FloatRegisters::Simd128}; static constexpr FloatRegister ScratchSimd128Reg = {FloatRegisters::v31, diff --git a/js/src/jit/arm64/CodeGenerator-arm64.cpp b/js/src/jit/arm64/CodeGenerator-arm64.cpp index ba85701c61eb..1f5774556c23 100644 --- a/js/src/jit/arm64/CodeGenerator-arm64.cpp +++ b/js/src/jit/arm64/CodeGenerator-arm64.cpp @@ -1969,7 +1969,7 @@ void CodeGenerator::visitWasmStackArg(LWasmStackArg* ins) { case MIRType::Float32: masm.storeFloat32(ToFloatRegister(ins->arg()), dst); return; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: masm.storeUnalignedSimd128(ToFloatRegister(ins->arg()), dst); return; @@ -2547,7 +2547,7 @@ void CodeGenerator::visitWasmSelect(LWasmSelect* lir) { masm.Fcsel(ARMFPRegister(outReg, 64), ARMFPRegister(trueReg, 64), ARMFPRegister(falseReg, 64), Assembler::NonZero); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: { MOZ_ASSERT(outReg == trueReg); Label done; @@ -3006,7 +3006,7 @@ void CodeGenerator::visitUModI64(LUModI64* lir) { } void CodeGenerator::visitSimd128(LSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD const LDefinition* out = ins->output(); masm.loadConstantSimd128(ins->simd128(), ToFloatRegister(out)); #else @@ -3015,7 +3015,7 @@ void CodeGenerator::visitSimd128(LSimd128* ins) { } void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD switch (ins->simdOp()) { case wasm::SimdOp::V128Bitselect: { FloatRegister lhs = ToFloatRegister(ins->v0()); @@ -3064,7 +3064,7 @@ void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) { } void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); FloatRegister rhs = ToFloatRegister(ins->rhs()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3469,7 +3469,7 @@ void CodeGenerator::visitWasmBinarySimd128WithConstant( void CodeGenerator::visitWasmVariableShiftSimd128( LWasmVariableShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); Register rhs = ToRegister(ins->rhs()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3521,7 +3521,7 @@ void CodeGenerator::visitWasmVariableShiftSimd128( void CodeGenerator::visitWasmConstantShiftSimd128( LWasmConstantShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); int32_t shift = ins->shift(); @@ -3584,7 +3584,7 @@ void CodeGenerator::visitWasmSignReplicationSimd128( } void CodeGenerator::visitWasmShuffleSimd128(LWasmShuffleSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); FloatRegister rhs = ToFloatRegister(ins->rhs()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3653,7 +3653,7 @@ void CodeGenerator::visitWasmShuffleSimd128(LWasmShuffleSimd128* ins) { } void CodeGenerator::visitWasmPermuteSimd128(LWasmPermuteSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); SimdConstant control = ins->control(); @@ -3762,7 +3762,7 @@ void CodeGenerator::visitWasmPermuteSimd128(LWasmPermuteSimd128* ins) { } void CodeGenerator::visitWasmReplaceLaneSimd128(LWasmReplaceLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ToFloatRegister(ins->lhs()) == ToFloatRegister(ins->output())); FloatRegister lhsDest = ToFloatRegister(ins->lhs()); const LAllocation* rhs = ins->rhs(); @@ -3816,7 +3816,7 @@ void CodeGenerator::visitWasmReplaceLaneSimd128(LWasmReplaceLaneSimd128* ins) { void CodeGenerator::visitWasmReplaceInt64LaneSimd128( LWasmReplaceInt64LaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_RELEASE_ASSERT(ins->mir()->simdOp() == wasm::SimdOp::I64x2ReplaceLane); MOZ_ASSERT(ToFloatRegister(ins->lhs()) == ToFloatRegister(ins->output())); masm.replaceLaneInt64x2(ins->mir()->laneIndex(), ToRegister64(ins->rhs()), @@ -3827,7 +3827,7 @@ void CodeGenerator::visitWasmReplaceInt64LaneSimd128( } void CodeGenerator::visitWasmScalarToSimd128(LWasmScalarToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister dest = ToFloatRegister(ins->output()); switch (ins->mir()->simdOp()) { @@ -3855,7 +3855,7 @@ void CodeGenerator::visitWasmScalarToSimd128(LWasmScalarToSimd128* ins) { } void CodeGenerator::visitWasmInt64ToSimd128(LWasmInt64ToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD Register64 src = ToRegister64(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3896,7 +3896,7 @@ void CodeGenerator::visitWasmInt64ToSimd128(LWasmInt64ToSimd128* ins) { } void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -4073,7 +4073,7 @@ void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) { } void CodeGenerator::visitWasmReduceSimd128(LWasmReduceSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); const LDefinition* dest = ins->output(); uint32_t imm = ins->mir()->imm(); @@ -4138,7 +4138,7 @@ void CodeGenerator::visitWasmReduceSimd128(LWasmReduceSimd128* ins) { void CodeGenerator::visitWasmReduceAndBranchSimd128( LWasmReduceAndBranchSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); ScratchSimd128Scope scratch(masm); @@ -4191,7 +4191,7 @@ void CodeGenerator::visitWasmReduceAndBranchSimd128( void CodeGenerator::visitWasmReduceSimd128ToInt64( LWasmReduceSimd128ToInt64* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); Register64 dest = ToOutRegister64(ins); uint32_t imm = ins->mir()->imm(); @@ -4216,7 +4216,7 @@ static inline wasm::MemoryAccessDesc DeriveMemoryAccessDesc( } void CodeGenerator::visitWasmLoadLaneSimd128(LWasmLoadLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Forward loading to wasmLoad, and use replaceLane after that. const MWasmLoadLaneSimd128* mir = ins->mir(); Register memoryBase = ToRegister(ins->memoryBase()); @@ -4259,7 +4259,7 @@ void CodeGenerator::visitWasmLoadLaneSimd128(LWasmLoadLaneSimd128* ins) { } void CodeGenerator::visitWasmStoreLaneSimd128(LWasmStoreLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Forward storing to wasmStore for the result of extractLane. const MWasmStoreLaneSimd128* mir = ins->mir(); Register memoryBase = ToRegister(ins->memoryBase()); diff --git a/js/src/jit/arm64/Lowering-arm64.cpp b/js/src/jit/arm64/Lowering-arm64.cpp index bedb93476969..88674bc63c36 100644 --- a/js/src/jit/arm64/Lowering-arm64.cpp +++ b/js/src/jit/arm64/Lowering-arm64.cpp @@ -519,7 +519,7 @@ void LIRGeneratorARM64::lowerBigIntPtrMod(MBigIntPtrMod* ins) { define(lir, ins); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool LIRGeneratorARM64::canFoldReduceSimd128AndBranch(wasm::SimdOp op) { switch (op) { @@ -1041,7 +1041,7 @@ void LIRGenerator::visitSignExtendInt64(MSignExtendInt64* ins) { } void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->v0()->type() == MIRType::Simd128); MOZ_ASSERT(ins->v1()->type() == MIRType::Simd128); MOZ_ASSERT(ins->v2()->type() == MIRType::Simd128); @@ -1095,7 +1095,7 @@ void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) { } void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* lhs = ins->lhs(); MDefinition* rhs = ins->rhs(); wasm::SimdOp op = ins->simdOp(); @@ -1120,7 +1120,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { #endif } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { return false; @@ -1141,7 +1141,7 @@ void LIRGenerator::visitWasmBinarySimd128WithConstant( } void LIRGenerator::visitWasmShiftSimd128(MWasmShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* lhs = ins->lhs(); MDefinition* rhs = ins->rhs(); @@ -1198,7 +1198,7 @@ void LIRGenerator::visitWasmShiftSimd128(MWasmShiftSimd128* ins) { } void LIRGenerator::visitWasmShuffleSimd128(MWasmShuffleSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->lhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->rhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1264,7 +1264,7 @@ void LIRGenerator::visitWasmShuffleSimd128(MWasmShuffleSimd128* ins) { } void LIRGenerator::visitWasmReplaceLaneSimd128(MWasmReplaceLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->lhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1290,7 +1290,7 @@ void LIRGenerator::visitWasmReplaceLaneSimd128(MWasmReplaceLaneSimd128* ins) { } void LIRGenerator::visitWasmScalarToSimd128(MWasmScalarToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->type() == MIRType::Simd128); switch (ins->input()->type()) { @@ -1324,7 +1324,7 @@ void LIRGenerator::visitWasmScalarToSimd128(MWasmScalarToSimd128* ins) { } void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->input()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1400,7 +1400,7 @@ void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) { } void LIRGenerator::visitWasmReduceSimd128(MWasmReduceSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (canEmitWasmReduceSimd128AtUses(ins)) { emitAtUses(ins); return; @@ -1449,7 +1449,7 @@ void LIRGenerator::visitWasmReduceSimd128(MWasmReduceSimd128* ins) { } void LIRGenerator::visitWasmLoadLaneSimd128(MWasmLoadLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // On 64-bit systems, the base pointer can be 32 bits or 64 bits. Either way, // it fits in a GPR so we can ignore the Register/Register64 distinction here. @@ -1471,7 +1471,7 @@ void LIRGenerator::visitWasmLoadLaneSimd128(MWasmLoadLaneSimd128* ins) { } void LIRGenerator::visitWasmStoreLaneSimd128(MWasmStoreLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // See comment above about the base pointer. LUse base = useRegisterAtStart(ins->base()); diff --git a/js/src/jit/arm64/Lowering-arm64.h b/js/src/jit/arm64/Lowering-arm64.h index af379933b9b7..3829b4d6893b 100644 --- a/js/src/jit/arm64/Lowering-arm64.h +++ b/js/src/jit/arm64/Lowering-arm64.h @@ -102,7 +102,7 @@ class LIRGeneratorARM64 : public LIRGeneratorShared { void lowerAtomicLoad64(MLoadUnboxedScalar* ins); void lowerAtomicStore64(MStoreUnboxedScalar* ins); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool canFoldReduceSimd128AndBranch(wasm::SimdOp op); bool canEmitWasmReduceSimd128AtUses(MWasmReduceSimd128* ins); #endif diff --git a/js/src/jit/arm64/MacroAssembler-arm64.cpp b/js/src/jit/arm64/MacroAssembler-arm64.cpp index 56cc116500b2..8188ba444345 100644 --- a/js/src/jit/arm64/MacroAssembler-arm64.cpp +++ b/js/src/jit/arm64/MacroAssembler-arm64.cpp @@ -179,7 +179,7 @@ void MacroAssemblerCompat::boxValue(Register type, Register src, Operand(ARMRegister(dest, 64), vixl::LSL, JSVAL_TAG_SHIFT)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MacroAssembler::MustMaskShiftCountSimd128(wasm::SimdOp op, int32_t* mask) { switch (op) { case wasm::SimdOp::I8x16Shl: diff --git a/js/src/jit/loong64/Architecture-loong64.cpp b/js/src/jit/loong64/Architecture-loong64.cpp index fbe4dad8d58b..e7a94ed8a309 100644 --- a/js/src/jit/loong64/Architecture-loong64.cpp +++ b/js/src/jit/loong64/Architecture-loong64.cpp @@ -32,7 +32,7 @@ FloatRegisters::Code FloatRegisters::FromName(const char* name) { } FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -44,7 +44,7 @@ FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) { } uint32_t FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -52,7 +52,7 @@ uint32_t FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { } uint32_t FloatRegister::getRegisterDumpOffsetInBytes() { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/loong64/Lowering-loong64.cpp b/js/src/jit/loong64/Lowering-loong64.cpp index 68927939d9e9..84aca4bbb9e4 100644 --- a/js/src/jit/loong64/Lowering-loong64.cpp +++ b/js/src/jit/loong64/Lowering-loong64.cpp @@ -933,7 +933,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { MOZ_CRASH("binary SIMD NYI"); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { return false; diff --git a/js/src/jit/loong64/MacroAssembler-loong64.cpp b/js/src/jit/loong64/MacroAssembler-loong64.cpp index 67e9bccfd57f..0824fef58c71 100644 --- a/js/src/jit/loong64/MacroAssembler-loong64.cpp +++ b/js/src/jit/loong64/MacroAssembler-loong64.cpp @@ -2703,7 +2703,7 @@ void MacroAssembler::PushRegsInMask(LiveRegisterSet set) { storePtr(*iter, Address(StackPointer, diff)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -2728,7 +2728,7 @@ void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, } } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -2759,7 +2759,7 @@ void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, } MOZ_ASSERT(diffG == 0); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/mips-shared/Lowering-mips-shared.cpp b/js/src/jit/mips-shared/Lowering-mips-shared.cpp index f5e0ba8d2050..36065bb13457 100644 --- a/js/src/jit/mips-shared/Lowering-mips-shared.cpp +++ b/js/src/jit/mips-shared/Lowering-mips-shared.cpp @@ -808,7 +808,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { MOZ_CRASH("binary SIMD NYI"); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { return false; diff --git a/js/src/jit/mips64/Architecture-mips64.cpp b/js/src/jit/mips64/Architecture-mips64.cpp index 89ddd4146f1d..cbbd56228786 100644 --- a/js/src/jit/mips64/Architecture-mips64.cpp +++ b/js/src/jit/mips64/Architecture-mips64.cpp @@ -52,7 +52,7 @@ FloatRegister FloatRegister::doubleOverlay() const { } FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -69,7 +69,7 @@ FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) { } uint32_t FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/mips64/MacroAssembler-mips64.cpp b/js/src/jit/mips64/MacroAssembler-mips64.cpp index d971d356a7af..52ed9fbaad51 100644 --- a/js/src/jit/mips64/MacroAssembler-mips64.cpp +++ b/js/src/jit/mips64/MacroAssembler-mips64.cpp @@ -2523,7 +2523,7 @@ void MacroAssembler::PushRegsInMask(LiveRegisterSet set) { storePtr(*iter, Address(StackPointer, diff)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -2548,7 +2548,7 @@ void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, } } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -2579,7 +2579,7 @@ void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, } MOZ_ASSERT(diffG == 0); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/riscv64/Architecture-riscv64.cpp b/js/src/jit/riscv64/Architecture-riscv64.cpp index 785c04afa292..bcbafe0eb328 100644 --- a/js/src/jit/riscv64/Architecture-riscv64.cpp +++ b/js/src/jit/riscv64/Architecture-riscv64.cpp @@ -32,7 +32,7 @@ FloatRegisters::Code FloatRegisters::FromName(const char* name) { } FloatRegisterSet FloatRegister::ReduceSetForPush(const FloatRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -66,7 +66,7 @@ FloatRegister FloatRegister::doubleOverlay() const { uint32_t FloatRegister::GetPushSizeInBytes( const TypedRegisterSet& s) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/riscv64/Architecture-riscv64.h b/js/src/jit/riscv64/Architecture-riscv64.h index f346726f6ea6..a13750f511a2 100644 --- a/js/src/jit/riscv64/Architecture-riscv64.h +++ b/js/src/jit/riscv64/Architecture-riscv64.h @@ -439,7 +439,7 @@ struct FloatRegister { const TypedRegisterSet& s); uint32_t getRegisterDumpOffsetInBytes() { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/riscv64/Lowering-riscv64.cpp b/js/src/jit/riscv64/Lowering-riscv64.cpp index 1b39442979b8..0156ede1842d 100644 --- a/js/src/jit/riscv64/Lowering-riscv64.cpp +++ b/js/src/jit/riscv64/Lowering-riscv64.cpp @@ -939,7 +939,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { MOZ_CRASH("binary SIMD NYI"); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { return false; diff --git a/js/src/jit/riscv64/MacroAssembler-riscv64.cpp b/js/src/jit/riscv64/MacroAssembler-riscv64.cpp index f9c6060c5599..1f33c7dbf4c6 100644 --- a/js/src/jit/riscv64/MacroAssembler-riscv64.cpp +++ b/js/src/jit/riscv64/MacroAssembler-riscv64.cpp @@ -3981,7 +3981,7 @@ void MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, } } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -4065,7 +4065,7 @@ void MacroAssembler::PushRegsInMask(LiveRegisterSet set) { storePtr(*iter, Address(StackPointer, diff)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif @@ -4240,7 +4240,7 @@ void MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, } MOZ_ASSERT(diffG == 0); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # error "Needs more careful logic if SIMD is enabled" #endif diff --git a/js/src/jit/riscv64/Register-riscv64.h b/js/src/jit/riscv64/Register-riscv64.h index c626c2802c5b..db9d129c43a8 100644 --- a/js/src/jit/riscv64/Register-riscv64.h +++ b/js/src/jit/riscv64/Register-riscv64.h @@ -90,7 +90,7 @@ static constexpr Register64 ReturnReg64(ReturnReg); static constexpr FloatRegister ReturnFloat32Reg{FloatRegisters::fa0, FloatRegisters::Single}; static constexpr FloatRegister ReturnDoubleReg{FloatRegisters::fa0}; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static constexpr FloatRegister ReturnSimd128Reg{FloatRegisters::invalid_reg}; static constexpr FloatRegister ScratchSimd128Reg{FloatRegisters::invalid_reg}; #endif diff --git a/js/src/jit/shared/CodeGenerator-shared.cpp b/js/src/jit/shared/CodeGenerator-shared.cpp index cc56775021a7..ada87f1f11a2 100644 --- a/js/src/jit/shared/CodeGenerator-shared.cpp +++ b/js/src/jit/shared/CodeGenerator-shared.cpp @@ -84,7 +84,7 @@ CodeGeneratorShared::CodeGeneratorShared(MIRGenerator* gen, LIRGraph* graph, frameDepth_ = AlignBytes(graph->localSlotsSize(), sizeof(uintptr_t)); #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) || \ defined(JS_CODEGEN_ARM64) // On X64/x86 and ARM64, we don't need alignment for Wasm SIMD at this time. diff --git a/js/src/jit/shared/Lowering-shared-inl.h b/js/src/jit/shared/Lowering-shared-inl.h index 940373b9a204..bdcc1da7d41a 100644 --- a/js/src/jit/shared/Lowering-shared-inl.h +++ b/js/src/jit/shared/Lowering-shared-inl.h @@ -292,7 +292,7 @@ void LIRGeneratorShared::defineReturn(LInstruction* lir, MDefinition* mir) { LFloatReg(ReturnDoubleReg))); break; case MIRType::Simd128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD lir->setDef(0, LDefinition(vreg, LDefinition::SIMD128, LFloatReg(ReturnSimd128Reg))); break; @@ -653,7 +653,7 @@ LDefinition LIRGeneratorShared::tempDouble() { return temp(LDefinition::DOUBLE); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD LDefinition LIRGeneratorShared::tempSimd128() { return temp(LDefinition::SIMD128); } diff --git a/js/src/jit/shared/Lowering-shared.h b/js/src/jit/shared/Lowering-shared.h index 5e7a15da83a1..bca860805e54 100644 --- a/js/src/jit/shared/Lowering-shared.h +++ b/js/src/jit/shared/Lowering-shared.h @@ -187,7 +187,7 @@ class LIRGeneratorShared { inline LBoxDefinition tempBox(); inline LDefinition tempFloat32(); inline LDefinition tempDouble(); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline LDefinition tempSimd128(); #endif inline LDefinition tempCopy(MDefinition* input, uint32_t reusedInput); diff --git a/js/src/jit/x64/Lowering-x64.cpp b/js/src/jit/x64/Lowering-x64.cpp index 705bb9863eb8..db62ef9a8c1a 100644 --- a/js/src/jit/x64/Lowering-x64.cpp +++ b/js/src/jit/x64/Lowering-x64.cpp @@ -374,7 +374,7 @@ void LIRGenerator::visitWasmStore(MWasmStore* ins) { valueAlloc = useRegisterAtStart(value); break; case Scalar::Simd128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD valueAlloc = useRegisterAtStart(value); break; #else diff --git a/js/src/jit/x64/Trampoline-x64.cpp b/js/src/jit/x64/Trampoline-x64.cpp index 3d87077be999..0a03eac5fb70 100644 --- a/js/src/jit/x64/Trampoline-x64.cpp +++ b/js/src/jit/x64/Trampoline-x64.cpp @@ -310,7 +310,7 @@ JitRuntime::getCppEntryRegisters(JitFrameLayout* frameStackAddress) { // Push AllRegs in a way that is compatible with RegisterDump, regardless of // what PushRegsInMask might do to reduce the set size. static void DumpAllRegs(MacroAssembler& masm) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD masm.PushRegsInMask(AllRegs); #else // When SIMD isn't supported, PushRegsInMask reduces the set of float diff --git a/js/src/jit/x86-shared/Architecture-x86-shared.cpp b/js/src/jit/x86-shared/Architecture-x86-shared.cpp index 4163cc05a5d6..b569fa99c5ba 100644 --- a/js/src/jit/x86-shared/Architecture-x86-shared.cpp +++ b/js/src/jit/x86-shared/Architecture-x86-shared.cpp @@ -42,7 +42,7 @@ js::jit::FloatRegisterSet js::jit::FloatRegister::ReduceSetForPush( SetType bits = s.bits(); // Ignore all SIMD register, if not supported. -#ifndef ENABLE_JIT_SIMD +#ifndef ENABLE_WASM_SIMD bits &= Codes::AllPhysMask * Codes::SpreadScalar; #endif diff --git a/js/src/jit/x86-shared/Assembler-x86-shared.cpp b/js/src/jit/x86-shared/Assembler-x86-shared.cpp index 22b8f22e6a14..c7f4bbbc974c 100644 --- a/js/src/jit/x86-shared/Assembler-x86-shared.cpp +++ b/js/src/jit/x86-shared/Assembler-x86-shared.cpp @@ -212,7 +212,7 @@ AssemblerX86Shared::DoubleCondition AssemblerX86Shared::InvertCondition( CPUInfo::SSEVersion CPUInfo::maxSSEVersion = UnknownSSE; CPUInfo::SSEVersion CPUInfo::maxEnabledSSEVersion = UnknownSSE; bool CPUInfo::avxPresent = false; -#ifdef ENABLE_JIT_AVX +#ifdef ENABLE_WASM_AVX bool CPUInfo::avxEnabled = true; #else bool CPUInfo::avxEnabled = false; diff --git a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp index a926d52b1cff..d915cf4e0434 100644 --- a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp +++ b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp @@ -243,7 +243,7 @@ void CodeGenerator::visitWasmStackArg(LWasmStackArg* ins) { case MIRType::Float32: masm.storeFloat32(ToFloatRegister(ins->arg()), dst); return; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: masm.storeUnalignedSimd128(ToFloatRegister(ins->arg()), dst); return; @@ -2152,7 +2152,7 @@ Operand CodeGeneratorX86Shared::toMemoryAccessOperand(T* lir, int32_t disp) { } void CodeGenerator::visitSimd128(LSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD const LDefinition* out = ins->output(); masm.loadConstantSimd128(ins->simd128(), ToFloatRegister(out)); #else @@ -2161,7 +2161,7 @@ void CodeGenerator::visitSimd128(LSimd128* ins) { } void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD switch (ins->simdOp()) { case wasm::SimdOp::V128Bitselect: { FloatRegister lhsDest = ToFloatRegister(ins->v0()); @@ -2212,7 +2212,7 @@ void CodeGenerator::visitWasmTernarySimd128(LWasmTernarySimd128* ins) { } void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); FloatRegister rhs = ToFloatRegister(ins->rhs()); FloatRegister temp1 = ToTempFloatRegisterOrInvalid(ins->temp0()); @@ -2612,7 +2612,7 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) { void CodeGenerator::visitWasmBinarySimd128WithConstant( LWasmBinarySimd128WithConstant* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); const SimdConstant& rhs = ins->rhs(); FloatRegister dest = ToFloatRegister(ins->output()); @@ -2830,7 +2830,7 @@ void CodeGenerator::visitWasmBinarySimd128WithConstant( void CodeGenerator::visitWasmVariableShiftSimd128( LWasmVariableShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhsDest = ToFloatRegister(ins->lhs()); Register rhs = ToRegister(ins->rhs()); FloatRegister temp = ToTempFloatRegisterOrInvalid(ins->temp0()); @@ -2884,7 +2884,7 @@ void CodeGenerator::visitWasmVariableShiftSimd128( void CodeGenerator::visitWasmConstantShiftSimd128( LWasmConstantShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); int32_t shift = ins->shift(); @@ -2941,7 +2941,7 @@ void CodeGenerator::visitWasmConstantShiftSimd128( void CodeGenerator::visitWasmSignReplicationSimd128( LWasmSignReplicationSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -2967,7 +2967,7 @@ void CodeGenerator::visitWasmSignReplicationSimd128( } void CodeGenerator::visitWasmShuffleSimd128(LWasmShuffleSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhsDest = ToFloatRegister(ins->lhs()); FloatRegister rhs = ToFloatRegister(ins->rhs()); SimdConstant control = ins->control(); @@ -3045,7 +3045,7 @@ void CodeGenerator::visitWasmShuffleSimd128(LWasmShuffleSimd128* ins) { #endif } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD enum PermuteX64I16x8Action : uint16_t { UNAVAILABLE = 0, @@ -3132,7 +3132,7 @@ static PermuteX64I16x8Action CalculateX64Permute16x8(SimdConstant* control) { #endif void CodeGenerator::visitWasmPermuteSimd128(LWasmPermuteSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); SimdConstant control = ins->control(); @@ -3309,7 +3309,7 @@ void CodeGenerator::visitWasmPermuteSimd128(LWasmPermuteSimd128* ins) { } void CodeGenerator::visitWasmReplaceLaneSimd128(LWasmReplaceLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister lhs = ToFloatRegister(ins->lhs()); FloatRegister dest = ToFloatRegister(ins->output()); const LAllocation* rhs = ins->rhs(); @@ -3341,7 +3341,7 @@ void CodeGenerator::visitWasmReplaceLaneSimd128(LWasmReplaceLaneSimd128* ins) { void CodeGenerator::visitWasmReplaceInt64LaneSimd128( LWasmReplaceInt64LaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_RELEASE_ASSERT(ins->mir()->simdOp() == wasm::SimdOp::I64x2ReplaceLane); masm.replaceLaneInt64x2(ins->mir()->laneIndex(), ToFloatRegister(ins->lhs()), ToRegister64(ins->rhs()), @@ -3352,7 +3352,7 @@ void CodeGenerator::visitWasmReplaceInt64LaneSimd128( } void CodeGenerator::visitWasmScalarToSimd128(LWasmScalarToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister dest = ToFloatRegister(ins->output()); switch (ins->mir()->simdOp()) { @@ -3380,7 +3380,7 @@ void CodeGenerator::visitWasmScalarToSimd128(LWasmScalarToSimd128* ins) { } void CodeGenerator::visitWasmInt64ToSimd128(LWasmInt64ToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD Register64 src = ToRegister64(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3421,7 +3421,7 @@ void CodeGenerator::visitWasmInt64ToSimd128(LWasmInt64ToSimd128* ins) { } void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); FloatRegister dest = ToFloatRegister(ins->output()); @@ -3599,7 +3599,7 @@ void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) { } void CodeGenerator::visitWasmReduceSimd128(LWasmReduceSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); const LDefinition* dest = ins->output(); uint32_t imm = ins->mir()->imm(); @@ -3663,7 +3663,7 @@ void CodeGenerator::visitWasmReduceSimd128(LWasmReduceSimd128* ins) { void CodeGenerator::visitWasmReduceAndBranchSimd128( LWasmReduceAndBranchSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); switch (ins->simdOp()) { @@ -3715,7 +3715,7 @@ void CodeGenerator::visitWasmReduceAndBranchSimd128( void CodeGenerator::visitWasmReduceSimd128ToInt64( LWasmReduceSimd128ToInt64* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD FloatRegister src = ToFloatRegister(ins->src()); Register64 dest = ToOutRegister64(ins); uint32_t imm = ins->mir()->imm(); @@ -3733,7 +3733,7 @@ void CodeGenerator::visitWasmReduceSimd128ToInt64( } void CodeGenerator::visitWasmLoadLaneSimd128(LWasmLoadLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD const MWasmLoadLaneSimd128* mir = ins->mir(); const wasm::MemoryAccessDesc& access = mir->access(); @@ -3784,7 +3784,7 @@ void CodeGenerator::visitWasmLoadLaneSimd128(LWasmLoadLaneSimd128* ins) { } void CodeGenerator::visitWasmStoreLaneSimd128(LWasmStoreLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD const MWasmStoreLaneSimd128* mir = ins->mir(); const wasm::MemoryAccessDesc& access = mir->access(); diff --git a/js/src/jit/x86-shared/Lowering-x86-shared.cpp b/js/src/jit/x86-shared/Lowering-x86-shared.cpp index 2990ac5cb9d8..f91a4f3ab354 100644 --- a/js/src/jit/x86-shared/Lowering-x86-shared.cpp +++ b/js/src/jit/x86-shared/Lowering-x86-shared.cpp @@ -738,7 +738,7 @@ void LIRGenerator::visitCopySign(MCopySign* ins) { // defineReuseInput. void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->v0()->type() == MIRType::Simd128); MOZ_ASSERT(ins->v1()->type() == MIRType::Simd128); MOZ_ASSERT(ins->v2()->type() == MIRType::Simd128); @@ -802,7 +802,7 @@ void LIRGenerator::visitWasmTernarySimd128(MWasmTernarySimd128* ins) { } void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* lhs = ins->lhs(); MDefinition* rhs = ins->rhs(); wasm::SimdOp op = ins->simdOp(); @@ -1069,7 +1069,7 @@ void LIRGenerator::visitWasmBinarySimd128(MWasmBinarySimd128* ins) { #endif } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MWasmTernarySimd128::specializeBitselectConstantMaskAsShuffle( int8_t shuffle[16]) { if (simdOp() != wasm::SimdOp::V128Bitselect) { @@ -1255,7 +1255,7 @@ bool MWasmBinarySimd128::specializeForConstantRhs() { void LIRGenerator::visitWasmBinarySimd128WithConstant( MWasmBinarySimd128WithConstant* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* lhs = ins->lhs(); MOZ_ASSERT(lhs->type() == MIRType::Simd128); @@ -1292,7 +1292,7 @@ void LIRGenerator::visitWasmBinarySimd128WithConstant( } void LIRGenerator::visitWasmShiftSimd128(MWasmShiftSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* lhs = ins->lhs(); MDefinition* rhs = ins->rhs(); @@ -1398,7 +1398,7 @@ void LIRGenerator::visitWasmShiftSimd128(MWasmShiftSimd128* ins) { } void LIRGenerator::visitWasmShuffleSimd128(MWasmShuffleSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->lhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->rhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1496,7 +1496,7 @@ void LIRGenerator::visitWasmShuffleSimd128(MWasmShuffleSimd128* ins) { } void LIRGenerator::visitWasmReplaceLaneSimd128(MWasmReplaceLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->lhs()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1533,7 +1533,7 @@ void LIRGenerator::visitWasmReplaceLaneSimd128(MWasmReplaceLaneSimd128* ins) { } void LIRGenerator::visitWasmScalarToSimd128(MWasmScalarToSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->type() == MIRType::Simd128); switch (ins->input()->type()) { @@ -1569,7 +1569,7 @@ void LIRGenerator::visitWasmScalarToSimd128(MWasmScalarToSimd128* ins) { } void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MOZ_ASSERT(ins->input()->type() == MIRType::Simd128); MOZ_ASSERT(ins->type() == MIRType::Simd128); @@ -1670,7 +1670,7 @@ void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) { } void LIRGenerator::visitWasmLoadLaneSimd128(MWasmLoadLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // A trick: On 32-bit systems, the base pointer is 32 bits (it was bounds // checked and then chopped). On 64-bit systems, it can be 32 bits or 64 // bits. Either way, it fits in a GPR so we can ignore the @@ -1691,7 +1691,7 @@ void LIRGenerator::visitWasmLoadLaneSimd128(MWasmLoadLaneSimd128* ins) { } void LIRGenerator::visitWasmStoreLaneSimd128(MWasmStoreLaneSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // See comment above. # ifndef JS_64BIT MOZ_ASSERT(ins->base()->type() == MIRType::Int32); @@ -1708,7 +1708,7 @@ void LIRGenerator::visitWasmStoreLaneSimd128(MWasmStoreLaneSimd128* ins) { #endif } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool LIRGeneratorX86Shared::canFoldReduceSimd128AndBranch(wasm::SimdOp op) { switch (op) { @@ -1751,10 +1751,10 @@ bool LIRGeneratorX86Shared::canEmitWasmReduceSimd128AtUses( return iter == ins->usesEnd(); } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD void LIRGenerator::visitWasmReduceSimd128(MWasmReduceSimd128* ins) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (canEmitWasmReduceSimd128AtUses(ins)) { emitAtUses(ins); return; diff --git a/js/src/jit/x86-shared/Lowering-x86-shared.h b/js/src/jit/x86-shared/Lowering-x86-shared.h index 8869a3ce3972..615584080850 100644 --- a/js/src/jit/x86-shared/Lowering-x86-shared.h +++ b/js/src/jit/x86-shared/Lowering-x86-shared.h @@ -53,7 +53,7 @@ class LIRGeneratorX86Shared : public LIRGeneratorShared { void lowerAtomicTypedArrayElementBinop(MAtomicTypedArrayElementBinop* ins, bool useI386ByteRegisters); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool isThreeOpAllowed() { return Assembler::HasAVX(); } bool canFoldReduceSimd128AndBranch(wasm::SimdOp op); bool canEmitWasmReduceSimd128AtUses(MWasmReduceSimd128* ins); diff --git a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp index 2f6a8b409acc..776e8e59145a 100644 --- a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp +++ b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp @@ -310,7 +310,7 @@ void MacroAssemblerX86Shared::minMaxFloat32(FloatRegister first, bind(&done); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool MacroAssembler::MustMaskShiftCountSimd128(wasm::SimdOp op, int32_t* mask) { switch (op) { case wasm::SimdOp::I8x16Shl: diff --git a/js/src/jit/x86/Lowering-x86.cpp b/js/src/jit/x86/Lowering-x86.cpp index 229c77fa044c..701198c3e9a5 100644 --- a/js/src/jit/x86/Lowering-x86.cpp +++ b/js/src/jit/x86/Lowering-x86.cpp @@ -497,7 +497,7 @@ void LIRGenerator::visitWasmStore(MWasmStore* ins) { } break; case Scalar::Simd128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD valueAlloc = useRegisterAtStart(ins->value()); break; #else diff --git a/js/src/jit/x86/Trampoline-x86.cpp b/js/src/jit/x86/Trampoline-x86.cpp index 627312f2eb1b..18dc08702b78 100644 --- a/js/src/jit/x86/Trampoline-x86.cpp +++ b/js/src/jit/x86/Trampoline-x86.cpp @@ -223,7 +223,7 @@ JitRuntime::getCppEntryRegisters(JitFrameLayout* frameStackAddress) { // Push AllRegs in a way that is compatible with RegisterDump, regardless of // what PushRegsInMask might do to reduce the set size. static void DumpAllRegs(MacroAssembler& masm) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD masm.PushRegsInMask(AllRegs); #else // When SIMD isn't supported, PushRegsInMask reduces the set of float diff --git a/js/src/shell/js.cpp b/js/src/shell/js.cpp index f958cef5a211..5b1ab1188735 100644 --- a/js/src/shell/js.cpp +++ b/js/src/shell/js.cpp @@ -13026,7 +13026,7 @@ bool InitOptionParser(OptionParser& op) { '\0', "no-sse42", "Pretend CPU does not support SSE4.2 instructions " "to test JIT codegen (no-op on platforms other than x86 and x64).") || -#ifdef ENABLE_JIT_AVX +#ifdef ENABLE_WASM_AVX !op.addBoolOption('\0', "enable-avx", "No-op. AVX is enabled by default, if available.") || !op.addBoolOption( diff --git a/js/src/vm/Initialization.cpp b/js/src/vm/Initialization.cpp index 52e91afd40e8..32f135baac1a 100644 --- a/js/src/vm/Initialization.cpp +++ b/js/src/vm/Initialization.cpp @@ -320,7 +320,7 @@ JS_PUBLIC_API bool JS_SetICUMemoryFunctions(JS_ICUAllocFn allocFn, #endif } -#if defined(ENABLE_JIT_SIMD) && \ +#if defined(ENABLE_WASM_SIMD) && \ (defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)) void JS::SetAVXEnabled(bool enabled) { if (enabled) { diff --git a/js/src/wasm/WasmBCClass.h b/js/src/wasm/WasmBCClass.h index b01f4b71ca85..4abcde369bb5 100644 --- a/js/src/wasm/WasmBCClass.h +++ b/js/src/wasm/WasmBCClass.h @@ -452,7 +452,7 @@ struct BaseCompiler final { inline bool isAvailablePtr(RegPtr r); inline bool isAvailableF32(RegF32 r); inline bool isAvailableF64(RegF64 r); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline bool isAvailableV128(RegV128 r); #endif @@ -463,7 +463,7 @@ struct BaseCompiler final { [[nodiscard]] inline RegPtr needPtr(); [[nodiscard]] inline RegF32 needF32(); [[nodiscard]] inline RegF64 needF64(); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] inline RegV128 needV128(); #endif @@ -474,7 +474,7 @@ struct BaseCompiler final { inline void needPtr(RegPtr specific); inline void needF32(RegF32 specific); inline void needF64(RegF64 specific); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void needV128(RegV128 specific); #endif @@ -501,7 +501,7 @@ struct BaseCompiler final { inline void freePtr(RegPtr r); inline void freeF32(RegF32 r); inline void freeF64(RegF64 r); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void freeV128(RegV128 r); #endif @@ -515,7 +515,7 @@ struct BaseCompiler final { inline void maybeFree(RegF64 r); inline void maybeFree(RegRef r); inline void maybeFree(RegPtr r); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void maybeFree(RegV128 r); #endif @@ -576,7 +576,7 @@ struct BaseCompiler final { inline void loadMemF32(const Stk& src, RegF32 dest); inline void loadLocalF32(const Stk& src, RegF32 dest); inline void loadRegisterF32(const Stk& src, RegF32 dest); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void loadConstV128(const Stk& src, RegV128 dest); inline void loadMemV128(const Stk& src, RegV128 dest); inline void loadLocalV128(const Stk& src, RegV128 dest); @@ -596,7 +596,7 @@ struct BaseCompiler final { #endif inline void loadF64(const Stk& src, RegF64 dest); inline void loadF32(const Stk& src, RegF32 dest); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void loadV128(const Stk& src, RegV128 dest); #endif inline void loadRef(const Stk& src, RegRef dest); @@ -665,7 +665,7 @@ struct BaseCompiler final { inline void pushPtr(RegPtr r); inline void pushF64(RegF64 r); inline void pushF32(RegF32 r); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void pushV128(RegV128 r); #endif @@ -683,7 +683,7 @@ struct BaseCompiler final { inline void pushPtr(intptr_t v); inline void pushF64(double v); inline void pushF32(float v); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void pushV128(V128 v); #endif inline void pushConstRef(intptr_t v); @@ -696,7 +696,7 @@ struct BaseCompiler final { inline void pushLocalRef(uint32_t slot); inline void pushLocalF64(uint32_t slot); inline void pushLocalF32(uint32_t slot); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void pushLocalV128(uint32_t slot); #endif @@ -718,7 +718,7 @@ struct BaseCompiler final { [[nodiscard]] inline RegI32 popI32(); inline RegI32 popI32(RegI32 specific); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Call only from other popV128() variants. v must be the stack top. May pop // the CPU stack. inline void popV128(const Stk& v, RegV128 dest); @@ -786,7 +786,7 @@ struct BaseCompiler final { inline void pop2xI64(RegI64* r0, RegI64* r1); inline void pop2xF32(RegF32* r0, RegF32* r1); inline void pop2xF64(RegF64* r0, RegF64* r1); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void pop2xV128(RegV128* r0, RegV128* r1); #endif inline void pop2xRef(RegRef* r0, RegRef* r1); @@ -1062,7 +1062,7 @@ struct BaseCompiler final { inline RegI64 captureReturnedI64(); inline RegF32 captureReturnedF32(const FunctionCall& call); inline RegF64 captureReturnedF64(const FunctionCall& call); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline RegV128 captureReturnedV128(const FunctionCall& call); #endif inline RegRef captureReturnedRef(); @@ -1077,7 +1077,7 @@ struct BaseCompiler final { inline void movePtr(RegPtr src, RegPtr dest); inline void moveF64(RegF64 src, RegF64 dest); inline void moveF32(RegF32 src, RegF32 dest); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void moveV128(RegV128 src, RegV128 dest); #endif @@ -1857,7 +1857,7 @@ struct BaseCompiler final { PreBarrierKind preBarrierKind, PostBarrierKind postBarrierKind); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void emitVectorAndNot(); # ifdef ENABLE_WASM_RELAXED_SIMD void emitDotI8x16I7x16AddS(); diff --git a/js/src/wasm/WasmBCCodegen-inl.h b/js/src/wasm/WasmBCCodegen-inl.h index ee949de088ff..151676c78c16 100644 --- a/js/src/wasm/WasmBCCodegen-inl.h +++ b/js/src/wasm/WasmBCCodegen-inl.h @@ -67,7 +67,7 @@ void BaseCompiler::moveF32(RegF32 src, RegF32 dest) { } } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::moveV128(RegV128 src, RegV128 dest) { if (src != dest) { masm.moveSimd128(src, dest); @@ -105,7 +105,7 @@ inline void BaseCompiler::move(RegPtr src, RegPtr dest) { movePtr(src, dest); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD template <> inline void BaseCompiler::move(RegV128 src, RegV128 dest) { moveV128(src, dest); @@ -189,7 +189,7 @@ RegF64 BaseCompiler::captureReturnedF64(const FunctionCall& call) { return r; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 BaseCompiler::captureReturnedV128(const FunctionCall& call) { RegV128 r = RegV128(ReturnSimd128Reg); MOZ_ASSERT(isAvailableV128(r)); diff --git a/js/src/wasm/WasmBCFrame.cpp b/js/src/wasm/WasmBCFrame.cpp index add424a017a4..fcfe8a4ee2e4 100644 --- a/js/src/wasm/WasmBCFrame.cpp +++ b/js/src/wasm/WasmBCFrame.cpp @@ -79,7 +79,7 @@ void BaseLocalIter::settle() { case MIRType::Double: case MIRType::Float32: case MIRType::WasmAnyRef: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: #endif if (argsIter_->argInRegister()) { @@ -109,7 +109,7 @@ void BaseLocalIter::settle() { case ValType::I64: case ValType::F32: case ValType::F64: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: #endif case ValType::Ref: @@ -309,7 +309,7 @@ bool StackMapGenerator::createStackMap( case Stk::ConstI64: case Stk::ConstF32: case Stk::ConstF64: -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case Stk::MemV128: case Stk::ConstV128: # endif @@ -319,7 +319,7 @@ bool StackMapGenerator::createStackMap( case Stk::LocalI64: case Stk::LocalF32: case Stk::LocalF64: -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case Stk::LocalV128: # endif // These also have uninteresting type. Check that they live in the @@ -331,7 +331,7 @@ bool StackMapGenerator::createStackMap( case Stk::RegisterI64: case Stk::RegisterF32: case Stk::RegisterF64: -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case Stk::RegisterV128: # endif // These also have uninteresting type, but more to the point: all diff --git a/js/src/wasm/WasmBCFrame.h b/js/src/wasm/WasmBCFrame.h index aa1a59e1877a..7965f55fb68f 100644 --- a/js/src/wasm/WasmBCFrame.h +++ b/js/src/wasm/WasmBCFrame.h @@ -659,7 +659,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { masm.loadFloat32(addressOfLocal(src), dest); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void loadLocalV128(const Local& src, RegV128 dest) { masm.loadUnalignedSimd128(addressOfLocal(src), dest); } @@ -685,7 +685,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { masm.storeFloat32(src, addressOfLocal(dest)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void storeLocalV128(RegV128 src, const Local& dest) { masm.storeUnalignedSimd128(src, addressOfLocal(dest)); } @@ -758,7 +758,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { static constexpr size_t StackSizeOfInt64 = ABIResult::StackSizeOfInt64; static constexpr size_t StackSizeOfFloat = ABIResult::StackSizeOfFloat; static constexpr size_t StackSizeOfDouble = ABIResult::StackSizeOfDouble; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static constexpr size_t StackSizeOfV128 = ABIResult::StackSizeOfV128; #endif @@ -790,7 +790,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { return currentStackHeight(); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD uint32_t pushV128(RegV128 r) { mozilla::DebugOnly stackBefore = currentStackHeight(); # ifdef RABALDR_CHUNKY_STACK @@ -854,7 +854,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { MOZ_ASSERT(stackBefore - StackSizeOfDouble == currentStackHeight()); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void popV128(RegV128 r) { mozilla::DebugOnly stackBefore = currentStackHeight(); masm.loadUnalignedSimd128(Address(sp_, stackOffset(currentStackHeight())), @@ -908,7 +908,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { masm.loadFloat32(Address(sp_, stackOffset(offset)), dest); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void loadStackV128(int32_t offset, RegV128 dest) { masm.loadUnalignedSimd128(Address(sp_, stackOffset(offset)), dest); } @@ -1090,7 +1090,7 @@ class BaseStackFrame final : public BaseStackFrameAllocator { store64BitsToStack(bits.i64, destHeight, temp); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void storeImmediateV128ToStack(V128 imm, uint32_t destHeight, Register temp) { union { int32_t i32[4]; diff --git a/js/src/wasm/WasmBCMemory.cpp b/js/src/wasm/WasmBCMemory.cpp index e6e76997a6dc..25304c2896bf 100644 --- a/js/src/wasm/WasmBCMemory.cpp +++ b/js/src/wasm/WasmBCMemory.cpp @@ -877,7 +877,7 @@ void BaseCompiler::doLoadCommon(MemoryAccessDesc* access, AccessCheck check, free(rp); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: { RegType rp = popMemoryAccess(access, &check); RegV128 rv = needV128(); @@ -967,7 +967,7 @@ void BaseCompiler::doStoreCommon(MemoryAccessDesc* access, AccessCheck check, free(rv); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: { RegV128 rv = popV128(); RegType rp = popMemoryAccess(access, &check); @@ -2477,7 +2477,7 @@ void BaseCompiler::memCopyInlineM32() { // Compute the number of copies of each width we will need to do size_t remainder = length; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD size_t numCopies16 = 0; if (MacroAssembler::SupportsFastUnalignedFPAccesses()) { numCopies16 = remainder / sizeof(V128); @@ -2500,7 +2500,7 @@ void BaseCompiler::memCopyInlineM32() { bool omitBoundsCheck = false; size_t offset = 0; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { RegI32 temp = needI32(); moveI32(src, temp); @@ -2655,7 +2655,7 @@ void BaseCompiler::memCopyInlineM32() { } #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { offset -= sizeof(V128); @@ -2696,7 +2696,7 @@ void BaseCompiler::memFillInlineM32() { // Compute the number of copies of each width we will need to do size_t remainder = length; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD size_t numCopies16 = 0; if (MacroAssembler::SupportsFastUnalignedFPAccesses()) { numCopies16 = remainder / sizeof(V128); @@ -2716,7 +2716,7 @@ void BaseCompiler::memFillInlineM32() { MOZ_ASSERT(numCopies2 <= 1 && numCopies1 <= 1); // Generate splatted definitions for wider fills as needed -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD V128 val16(value); #endif #ifdef JS_64BIT @@ -2801,7 +2801,7 @@ void BaseCompiler::memFillInlineM32() { } #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { offset -= sizeof(V128); @@ -2827,7 +2827,7 @@ void BaseCompiler::memFillInlineM32() { // // SIMD and Relaxed SIMD. -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::loadSplat(MemoryAccessDesc* access) { // We can implement loadSplat mostly as load + splat because the push of the // result onto the value stack in loadCommon normally will not generate any @@ -2971,7 +2971,7 @@ void BaseCompiler::storeLane(MemoryAccessDesc* access, uint32_t laneIndex) { storeCommon(access, AccessCheck(), type); } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD } // namespace wasm } // namespace js diff --git a/js/src/wasm/WasmBCRegDefs-inl.h b/js/src/wasm/WasmBCRegDefs-inl.h index 083a1647ec68..ecdc6a8b0a80 100644 --- a/js/src/wasm/WasmBCRegDefs-inl.h +++ b/js/src/wasm/WasmBCRegDefs-inl.h @@ -121,7 +121,7 @@ void BaseRegAlloc::needF64(RegF64 specific) { allocFPU(specific); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 BaseRegAlloc::needV128() { if (!hasFPU()) { bc->sync(); @@ -149,7 +149,7 @@ void BaseRegAlloc::freeF64(RegF64 r) { freeFPU(r); } void BaseRegAlloc::freeF32(RegF32 r) { freeFPU(r); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseRegAlloc::freeV128(RegV128 r) { freeFPU(r); } #endif diff --git a/js/src/wasm/WasmBCRegDefs.h b/js/src/wasm/WasmBCRegDefs.h index b6f756a440fe..bb84f0863de2 100644 --- a/js/src/wasm/WasmBCRegDefs.h +++ b/js/src/wasm/WasmBCRegDefs.h @@ -60,14 +60,14 @@ static constexpr FloatRegister RabaldrScratchF32{FloatRegisters::s30, FloatRegisters::Single}; static constexpr FloatRegister RabaldrScratchF64{FloatRegisters::d30, FloatRegisters::Double}; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD static constexpr FloatRegister RabaldrScratchV128{FloatRegisters::d30, FloatRegisters::Simd128}; # endif static_assert(RabaldrScratchF32 != ScratchFloat32Reg_, "Too busy"); static_assert(RabaldrScratchF64 != ScratchDoubleReg_, "Too busy"); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD static_assert(RabaldrScratchV128 != ScratchSimd128Reg, "Too busy"); # endif #endif @@ -130,7 +130,7 @@ static constexpr Register RabaldrScratchI32 = CallTempReg2; template struct RegTypeOf { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static_assert(t == MIRType::Float32 || t == MIRType::Double || t == MIRType::Simd128, "Float mask type"); @@ -148,7 +148,7 @@ template <> struct RegTypeOf { static constexpr RegTypeName value = RegTypeName::Float64; }; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD template <> struct RegTypeOf { static constexpr RegTypeName value = RegTypeName::Vector128; @@ -223,7 +223,7 @@ struct RegF64 : public FloatRegister { static RegF64 Invalid() { return RegF64(); } }; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD struct RegV128 : public FloatRegister { RegV128() {} explicit RegV128(FloatRegister reg) : FloatRegister(reg) { @@ -241,7 +241,7 @@ struct AnyReg { RegRef ref_; RegF32 f32_; RegF64 f64_; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 v128_; #endif }; @@ -252,7 +252,7 @@ struct AnyReg { REF, F32, F64, -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD V128 #endif } tag; @@ -273,7 +273,7 @@ struct AnyReg { tag = F64; f64_ = r; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD explicit AnyReg(RegV128 r) { tag = V128; v128_ = r; @@ -300,7 +300,7 @@ struct AnyReg { MOZ_ASSERT(tag == F64); return f64_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 v128() const { MOZ_ASSERT(tag == V128); return v128_; @@ -317,7 +317,7 @@ struct AnyReg { return AnyRegister(f32_); case F64: return AnyRegister(f64_); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case V128: return AnyRegister(v128_); #endif @@ -649,7 +649,7 @@ class BaseRegAlloc { bool isAvailableF64(RegF64 r) { return isAvailableFPU(r); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool isAvailableV128(RegV128 r) { return isAvailableFPU(r); } #endif @@ -671,7 +671,7 @@ class BaseRegAlloc { [[nodiscard]] inline RegF64 needF64(); inline void needF64(RegF64 specific); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] inline RegV128 needV128(); inline void needV128(RegV128 specific); #endif @@ -682,7 +682,7 @@ class BaseRegAlloc { inline void freePtr(RegPtr r); inline void freeF64(RegF64 r); inline void freeF32(RegF32 r); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline void freeV128(RegV128 r); #endif @@ -730,7 +730,7 @@ class BaseRegAlloc { void addKnownF64(RegF64 r) { knownFPU_.add(r); } -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD void addKnownV128(RegV128 r) { knownFPU_.add(r); } # endif @@ -767,7 +767,7 @@ class BaseScratchRegister { #endif }; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # ifdef RABALDR_SCRATCH_V128 class ScratchV128 : public BaseScratchRegister { public: diff --git a/js/src/wasm/WasmBCRegMgmt-inl.h b/js/src/wasm/WasmBCRegMgmt-inl.h index 801f5508c8bc..eddb6e08c269 100644 --- a/js/src/wasm/WasmBCRegMgmt-inl.h +++ b/js/src/wasm/WasmBCRegMgmt-inl.h @@ -29,7 +29,7 @@ bool BaseCompiler::isAvailableRef(RegRef r) { return ra.isAvailableRef(r); } bool BaseCompiler::isAvailablePtr(RegPtr r) { return ra.isAvailablePtr(r); } bool BaseCompiler::isAvailableF32(RegF32 r) { return ra.isAvailableF32(r); } bool BaseCompiler::isAvailableF64(RegF64 r) { return ra.isAvailableF64(r); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool BaseCompiler::isAvailableV128(RegV128 r) { return ra.isAvailableV128(r); } #endif @@ -39,7 +39,7 @@ bool BaseCompiler::isAvailableV128(RegV128 r) { return ra.isAvailableV128(r); } [[nodiscard]] RegPtr BaseCompiler::needPtr() { return ra.needPtr(); } [[nodiscard]] RegF32 BaseCompiler::needF32() { return ra.needF32(); } [[nodiscard]] RegF64 BaseCompiler::needF64() { return ra.needF64(); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] RegV128 BaseCompiler::needV128() { return ra.needV128(); } #endif @@ -49,7 +49,7 @@ void BaseCompiler::needRef(RegRef specific) { ra.needRef(specific); } void BaseCompiler::needPtr(RegPtr specific) { ra.needPtr(specific); } void BaseCompiler::needF32(RegF32 specific) { ra.needF32(specific); } void BaseCompiler::needF64(RegF64 specific) { ra.needF64(specific); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::needV128(RegV128 specific) { ra.needV128(specific); } #endif @@ -63,7 +63,7 @@ void BaseCompiler::freeRef(RegRef r) { ra.freeRef(r); } void BaseCompiler::freePtr(RegPtr r) { ra.freePtr(r); } void BaseCompiler::freeF32(RegF32 r) { ra.freeF32(r); } void BaseCompiler::freeF64(RegF64 r) { ra.freeF64(r); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::freeV128(RegV128 r) { ra.freeV128(r); } #endif @@ -84,7 +84,7 @@ void BaseCompiler::freeAny(AnyReg r) { case AnyReg::F64: freeF64(r.f64()); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case AnyReg::V128: freeV128(r.v128()); break; @@ -124,7 +124,7 @@ inline void BaseCompiler::free(RegF64 r) { freeF64(r); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD template <> inline void BaseCompiler::free(RegV128 r) { freeV128(r); @@ -182,7 +182,7 @@ void BaseCompiler::maybeFree(RegPtr r) { } } -#ifdef ENABLE_JIT_SIMD128 +#ifdef ENABLE_WASM_SIMD128 void BaseCompiler::maybeFree(RegV128 r) { if (r.isValid()) { freeV128(r); @@ -294,7 +294,7 @@ inline RegF64 BaseCompiler::pop() { return popF64(); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD template <> inline RegV128 BaseCompiler::need() { return needV128(); @@ -331,7 +331,7 @@ void BaseCompiler::needResultRegisters(ResultType type, ResultRegKind which) { needI64(RegI64(result.gpr64())); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (which == ResultRegKind::All) { needV128(RegV128(result.fpr())); } @@ -391,7 +391,7 @@ void BaseCompiler::freeResultRegisters(ResultType type, ResultRegKind which) { freeI64(RegI64(result.gpr64())); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (which == ResultRegKind::All) { freeV128(RegV128(result.fpr())); } diff --git a/js/src/wasm/WasmBCStk.h b/js/src/wasm/WasmBCStk.h index 06526a52608b..06a9529130ab 100644 --- a/js/src/wasm/WasmBCStk.h +++ b/js/src/wasm/WasmBCStk.h @@ -39,7 +39,7 @@ struct Stk { MemI64, // 64-bit integer stack value ("offs") MemF32, // 32-bit floating stack value ("offs") MemF64, // 64-bit floating stack value ("offs") -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MemV128, // 128-bit vector stack value ("offs") #endif MemRef, // reftype (pointer wide) stack value ("offs") @@ -50,7 +50,7 @@ struct Stk { LocalI64, // Local int64 var ("slot") LocalF32, // Local float32 var ("slot") LocalF64, // Local double var ("slot") -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD LocalV128, // Local v128 var ("slot") #endif LocalRef, // Local reftype (pointer wide) var ("slot") @@ -59,7 +59,7 @@ struct Stk { RegisterI64, // 64-bit integer register ("i64reg") RegisterF32, // 32-bit floating register ("f32reg") RegisterF64, // 64-bit floating register ("f64reg") -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegisterV128, // 128-bit vector register ("v128reg") #endif RegisterRef, // reftype (pointer wide) register ("refReg") @@ -68,7 +68,7 @@ struct Stk { ConstI64, // 64-bit integer constant ("i64val") ConstF32, // 32-bit floating constant ("f32val") ConstF64, // 64-bit floating constant ("f64val") -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD ConstV128, // 128-bit vector constant ("v128val") #endif ConstRef, // reftype (pointer wide) constant ("refval") @@ -89,7 +89,7 @@ struct Stk { RegRef refReg_; RegF32 f32reg_; RegF64 f64reg_; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 v128reg_; #endif int32_t i32val_; @@ -97,7 +97,7 @@ struct Stk { intptr_t refval_; float f32val_; double f64val_; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD V128 v128val_; #endif uint32_t slot_; @@ -109,7 +109,7 @@ struct Stk { explicit Stk(RegRef r) : kind_(RegisterRef), refReg_(r) {} explicit Stk(RegF32 r) : kind_(RegisterF32), f32reg_(r) {} explicit Stk(RegF64 r) : kind_(RegisterF64), f64reg_(r) {} -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD explicit Stk(RegV128 r) : kind_(RegisterV128), v128reg_(r) {} #endif explicit Stk(int32_t v) : kind_(ConstI32), i32val_(v) {} @@ -117,7 +117,7 @@ struct Stk { explicit Stk(int64_t v) : kind_(ConstI64), i64val_(v) {} explicit Stk(float v) : kind_(ConstF32), f32val_(v) {} explicit Stk(double v) : kind_(ConstF64), f64val_(v) {} -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD explicit Stk(V128 v) : kind_(ConstV128), v128val_(v) {} #endif explicit Stk(Kind k, uint32_t v) : kind_(k), slot_(v) { @@ -139,7 +139,7 @@ struct Stk { k = Stk::MemI64; break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD k = Stk::MemV128; break; #else @@ -190,7 +190,7 @@ struct Stk { MOZ_ASSERT(kind_ == RegisterF64); return f64reg_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 v128reg() const { MOZ_ASSERT(kind_ == RegisterV128); return v128reg_; @@ -222,7 +222,7 @@ struct Stk { *out = f64val_; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // For SIMD, do the same as for floats since we're using float registers to // hold vectors; this is just conservative. void v128val(V128* out) const { @@ -259,7 +259,7 @@ struct Stk { case MemF64: fprintf(stderr, "MemF64()"); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case MemV128: fprintf(stderr, "MemV128()"); break; @@ -279,7 +279,7 @@ struct Stk { case LocalF64: fprintf(stderr, "LocalF64()"); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case LocalV128: fprintf(stderr, "LocalV128()"); break; @@ -299,7 +299,7 @@ struct Stk { case RegisterF64: fprintf(stderr, "RegisterF64()"); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case RegisterV128: fprintf(stderr, "RegisterV128()"); break; @@ -319,7 +319,7 @@ struct Stk { case ConstF64: fprintf(stderr, "ConstF64()"); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case ConstV128: fprintf(stderr, "ConstV128()"); break; diff --git a/js/src/wasm/WasmBCStkMgmt-inl.h b/js/src/wasm/WasmBCStkMgmt-inl.h index 3b3d3c0266c4..b723873303b8 100644 --- a/js/src/wasm/WasmBCStkMgmt-inl.h +++ b/js/src/wasm/WasmBCStkMgmt-inl.h @@ -141,7 +141,7 @@ void BaseCompiler::loadRegisterF32(const Stk& src, RegF32 dest) { moveF32(src.f32reg(), dest); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::loadConstV128(const Stk& src, RegV128 dest) { V128 f; src.v128val(&f); @@ -277,7 +277,7 @@ void BaseCompiler::loadF32(const Stk& src, RegF32 dest) { } } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::loadV128(const Stk& src, RegV128 dest) { switch (src.kind()) { case Stk::ConstV128: @@ -426,7 +426,7 @@ void BaseCompiler::sync() { v.setOffs(Stk::MemF32, offs); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::LocalV128: { ScratchV128 scratch(*this); loadV128(v, scratch); @@ -511,7 +511,7 @@ void BaseCompiler::pushAny(AnyReg r) { pushF64(r.f64()); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case AnyReg::V128: { pushV128(r.v128()); break; @@ -558,7 +558,7 @@ void BaseCompiler::pushF32(RegF32 r) { push(Stk(r)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::pushV128(RegV128 r) { MOZ_ASSERT(!isAvailableV128(r)); push(Stk(r)); @@ -588,7 +588,7 @@ void BaseCompiler::pushF64(double v) { push(Stk(v)); } void BaseCompiler::pushF32(float v) { push(Stk(v)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::pushV128(V128 v) { push(Stk(v)); } #endif @@ -616,7 +616,7 @@ void BaseCompiler::pushLocalF32(uint32_t slot) { stk_.infallibleEmplaceBack(Stk(Stk::LocalF32, slot)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::pushLocalV128(uint32_t slot) { stk_.infallibleEmplaceBack(Stk(Stk::LocalV128, slot)); } @@ -654,7 +654,7 @@ AnyReg BaseCompiler::popAny(AnyReg specific) { case Stk::ConstF64: return AnyReg(popF64(specific.f64())); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::MemV128: case Stk::LocalV128: case Stk::RegisterV128: @@ -702,7 +702,7 @@ AnyReg BaseCompiler::popAny() { case Stk::ConstF64: return AnyReg(popF64()); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::MemV128: case Stk::LocalV128: case Stk::RegisterV128: @@ -780,7 +780,7 @@ RegI32 BaseCompiler::popI32(RegI32 specific) { return specific; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Call only from other popV128() variants. // v must be the stack top. May pop the CPU stack. @@ -1082,7 +1082,7 @@ bool BaseCompiler::hasConst() const { case Stk::ConstI64: case Stk::ConstF32: case Stk::ConstF64: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::ConstV128: #endif case Stk::ConstRef: @@ -1192,7 +1192,7 @@ void BaseCompiler::pop2xF64(RegF64* r0, RegF64* r1) { *r0 = popF64(); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD void BaseCompiler::pop2xV128(RegV128* r0, RegV128* r1) { *r1 = popV128(); *r0 = popV128(); @@ -1304,7 +1304,7 @@ size_t BaseCompiler::stackConsumed(size_t numval) { case Stk::MemF32: size += BaseStackFrame::StackSizeOfFloat; break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::MemV128: size += BaseStackFrame::StackSizeOfV128; break; @@ -1332,7 +1332,7 @@ void BaseCompiler::popValueStackTo(uint32_t stackSize) { case Stk::RegisterF32: freeF32(v.f32reg()); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::RegisterV128: freeV128(v.v128reg()); break; diff --git a/js/src/wasm/WasmBaselineCompile.cpp b/js/src/wasm/WasmBaselineCompile.cpp index 72e76274df9e..a91b6bcc5b32 100644 --- a/js/src/wasm/WasmBaselineCompile.cpp +++ b/js/src/wasm/WasmBaselineCompile.cpp @@ -653,7 +653,7 @@ bool BaseCompiler::beginFunction() { case MIRType::Float32: fr.storeLocalF32(RegF32(i->fpu()), l); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: fr.storeLocalV128(RegV128(i->fpu()), l); break; @@ -1034,7 +1034,7 @@ void BaseCompiler::saveRegisterReturnValues(const ResultType& resultType) { break; } case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD masm.storeUnalignedSimd128(RegV128(result.fpr()), dest); break; #else @@ -1079,7 +1079,7 @@ void BaseCompiler::restoreRegisterReturnValues(const ResultType& resultType) { masm.loadPtr(src, RegRef(result.gpr())); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD masm.loadUnalignedSimd128(src, RegV128(result.fpr())); break; #else @@ -1295,7 +1295,7 @@ void BaseCompiler::popRegisterResults(ABIResultIter& iter) { popRef(RegRef(result.gpr())); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD popV128(RegV128(result.fpr())); #else MOZ_CRASH("No SIMD support"); @@ -1419,7 +1419,7 @@ void BaseCompiler::popStackResults(ABIResultIter& iter, StackHeight stackBase) { case Stk::ConstF64: fr.storeImmediateF64ToStack(v.f64val_, resultHeight, temp); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case Stk::ConstV128: fr.storeImmediateV128ToStack(v.v128val_, resultHeight, temp); break; @@ -1546,7 +1546,7 @@ bool BaseCompiler::pushResults(ResultType type, StackHeight resultsBase) { pushI64(RegI64(result.gpr64())); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD pushV128(RegV128(result.fpr())); break; #else @@ -1749,7 +1749,7 @@ void BaseCompiler::passArg(ValType type, const Stk& arg, FunctionCall* call) { break; } case ValType::V128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD ABIArg argLoc = call->abi.next(MIRType::Simd128); switch (argLoc.kind()) { case ABIArg::Stack: { @@ -1992,7 +1992,7 @@ void BaseCompiler::pushBuiltinCallResult(const FunctionCall& call, pushF64(rv); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: { RegV128 rv = captureReturnedV128(call); pushV128(rv); @@ -4727,7 +4727,7 @@ bool BaseCompiler::emitTryTable() { break; } case ValType::V128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 reg = needV128(); masm.loadUnalignedSimd128(Address(data, offset), reg); pushV128(reg); @@ -4944,7 +4944,7 @@ bool BaseCompiler::emitCatch() { break; } case ValType::V128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 reg = needV128(); masm.loadUnalignedSimd128(Address(data, offset), reg); pushV128(reg); @@ -5241,7 +5241,7 @@ bool BaseCompiler::emitThrow() { break; } case ValType::V128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 reg = popV128(); masm.storeUnalignedSimd128(reg, Address(data, offset)); freeV128(reg); @@ -5959,7 +5959,7 @@ bool BaseCompiler::emitGetLocal() { pushLocalI64(slot); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD pushLocalV128(slot); break; #else @@ -6032,7 +6032,7 @@ bool BaseCompiler::emitSetOrTeeLocal(uint32_t slot) { break; } case ValType::V128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD RegV128 rv = popV128(); syncLocal(slot); fr.storeLocalV128(rv, localFromSlot(slot, MIRType::Simd128)); @@ -6110,7 +6110,7 @@ bool BaseCompiler::emitGetGlobal() { case ValType::Ref: pushRef(intptr_t(value.ref().forCompiledCode())); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: pushV128(value.v128()); break; @@ -6157,7 +6157,7 @@ bool BaseCompiler::emitGetGlobal() { pushRef(rv); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: { RegV128 rv = needV128(); ScratchPtr tmp(*this); @@ -6232,7 +6232,7 @@ bool BaseCompiler::emitSetGlobal() { freeRef(rv); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: { RegV128 rv = popV128(); ScratchPtr tmp(*this); @@ -6377,7 +6377,7 @@ bool BaseCompiler::emitSelect(bool typed) { pushF64(r); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: { RegV128 r, rs; pop2xV128(&r, &rs); @@ -7739,7 +7739,7 @@ void BaseCompiler::emitGcGet(StorageType type, FieldWideningOp wideningOp, pushF64(r); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case StorageType::V128: { MOZ_ASSERT(wideningOp == FieldWideningOp::None); RegV128 r = needV128(); @@ -7804,7 +7804,7 @@ void BaseCompiler::emitGcSetScalar(const T& dst, StorageType type, NullCheckPolicy::emitTrapSite(this, fco, TrapMachineInsn::Store64); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case StorageType::V128: { FaultingCodeOffset fco = masm.storeUnalignedSimd128(value.v128(), dst); NullCheckPolicy::emitTrapSite(this, fco, TrapMachineInsn::Store128); @@ -9244,7 +9244,7 @@ bool BaseCompiler::emitExternConvertAny() { // // SIMD and Relaxed SIMD. -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // Emitter trampolines used by abstracted SIMD operations. Naming here follows // the SIMD spec pretty closely. @@ -10477,7 +10477,7 @@ bool BaseCompiler::emitVectorLaneSelect() { return true; } # endif // ENABLE_WASM_RELAXED_SIMD -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD ////////////////////////////////////////////////////////////////////////////// // @@ -11395,7 +11395,7 @@ bool BaseCompiler::emitBody() { return iter_.unrecognizedOpcode(&op); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // SIMD operations case uint16_t(Op::SimdPrefix): { uint32_t laneIndex; @@ -12009,7 +12009,7 @@ bool BaseCompiler::emitBody() { } // switch (op.b1) return iter_.unrecognizedOpcode(&op); } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD // "Miscellaneous" operations case uint16_t(Op::MiscPrefix): { @@ -12387,7 +12387,7 @@ void BaseCompiler::assertResultRegistersAvailable(ResultType type) { MOZ_ASSERT(isAvailableI64(RegI64(result.gpr64()))); break; case ValType::V128: -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD MOZ_ASSERT(isAvailableV128(RegV128(result.fpr()))); break; # else @@ -12438,7 +12438,7 @@ void BaseCompiler::performRegisterLeakCheck() { case Stk::RegisterF64: check.addKnownF64(item.f64reg()); break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case Stk::RegisterV128: check.addKnownV128(item.v128reg()); break; @@ -12478,7 +12478,7 @@ void BaseCompiler::assertStackInvariants() const { case Stk::MemF32: size += BaseStackFrame::StackSizeOfFloat; break; -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD case Stk::MemV128: size += BaseStackFrame::StackSizeOfV128; break; diff --git a/js/src/wasm/WasmBinary.h b/js/src/wasm/WasmBinary.h index df67c06195a0..89b4e0b8c1cc 100644 --- a/js/src/wasm/WasmBinary.h +++ b/js/src/wasm/WasmBinary.h @@ -484,7 +484,7 @@ class Decoder { [[nodiscard]] bool readFixedU32(uint32_t* u) { return read(u); } [[nodiscard]] bool readFixedF32(float* f) { return read(f); } [[nodiscard]] bool readFixedF64(double* d) { return read(d); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] bool readFixedV128(V128* d) { for (unsigned i = 0; i < 16; i++) { if (!read(d->bytes + i)) { @@ -553,7 +553,7 @@ class Decoder { [[nodiscard]] bool readI64Const(int64_t* i64); [[nodiscard]] bool readF32Const(float* f32); [[nodiscard]] bool readF64Const(double* f64); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] bool readV128Const(V128* value); #endif [[nodiscard]] bool readRefNull(const TypeContext& types, @@ -748,7 +748,7 @@ inline bool Decoder::readPackedType(const TypeContext& types, } switch (code) { case uint8_t(TypeCode::V128): { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (!features.simd) { return fail("v128 not enabled"); } @@ -958,7 +958,7 @@ inline bool Decoder::readF64Const(double* f64) { return true; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD inline bool Decoder::readV128Const(V128* value) { if (!readFixedV128(value)) { return fail("unable to read V128 constant"); diff --git a/js/src/wasm/WasmDebugFrame.cpp b/js/src/wasm/WasmDebugFrame.cpp index 24bb7778a11e..ed11d606b3d0 100644 --- a/js/src/wasm/WasmDebugFrame.cpp +++ b/js/src/wasm/WasmDebugFrame.cpp @@ -117,7 +117,7 @@ bool DebugFrame::getLocal(uint32_t localIndex, MutableHandleValue vp) { case jit::MIRType::WasmAnyRef: vp.set(((AnyRef*)dataPtr)->toJSValue()); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case jit::MIRType::Simd128: vp.set(NumberValue(0)); break; diff --git a/js/src/wasm/WasmDebugFrame.h b/js/src/wasm/WasmDebugFrame.h index a34bcdb16b8b..56b492ef9482 100644 --- a/js/src/wasm/WasmDebugFrame.h +++ b/js/src/wasm/WasmDebugFrame.h @@ -52,7 +52,7 @@ class DebugFrame { int64_t i64_; float f32_; double f64_; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD V128 v128_; #endif AnyRef anyref_; @@ -108,7 +108,7 @@ class DebugFrame { // alignment. uint32_t padding_; #endif -#if defined(ENABLE_JIT_SIMD) && defined(JS_CODEGEN_ARM64) +#if defined(ENABLE_WASM_SIMD) && defined(JS_CODEGEN_ARM64) uint64_t padding_; #endif diff --git a/js/src/wasm/WasmFeatures.h b/js/src/wasm/WasmFeatures.h index af76ba6679bb..9d85eaeeec16 100644 --- a/js/src/wasm/WasmFeatures.h +++ b/js/src/wasm/WasmFeatures.h @@ -98,7 +98,7 @@ bool SimdAvailable(JSContext* cx); // Privileged content that can access experimental features. bool IsPrivilegedContext(JSContext* cx); -#if defined(ENABLE_JIT_SIMD) && defined(DEBUG) +#if defined(ENABLE_WASM_SIMD) && defined(DEBUG) // Report the result of a Simd simplification to the testing infrastructure. void ReportSimdAnalysis(const char* data); #endif diff --git a/js/src/wasm/WasmInitExpr.cpp b/js/src/wasm/WasmInitExpr.cpp index ed58e304f1c6..0bae432c0c4c 100644 --- a/js/src/wasm/WasmInitExpr.cpp +++ b/js/src/wasm/WasmInitExpr.cpp @@ -292,7 +292,7 @@ bool InitExprInterpreter::evaluate(JSContext* cx, Decoder& d) { } CHECK(evalF64Const(c)); } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case uint16_t(Op::SimdPrefix): { MOZ_RELEASE_ASSERT(op.b1 == uint32_t(SimdOp::V128Const)); V128 c; @@ -499,7 +499,7 @@ bool wasm::DecodeConstantExpression(Decoder& d, CodeMetadata* codeMeta, *literal = Some(LitVal(c)); break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case uint16_t(Op::SimdPrefix): { if (!codeMeta->simdAvailable()) { return d.fail("v128 not enabled"); diff --git a/js/src/wasm/WasmIonCompile.cpp b/js/src/wasm/WasmIonCompile.cpp index d5dd6fe856e4..9c79b9cf0704 100644 --- a/js/src/wasm/WasmIonCompile.cpp +++ b/js/src/wasm/WasmIonCompile.cpp @@ -622,7 +622,7 @@ class FunctionCompiler { for (size_t i = args.lengthWithoutStackResults(); i < locals_.length(); i++) { ValType slotValType = locals_[i]; -#ifndef ENABLE_JIT_SIMD +#ifndef ENABLE_WASM_SIMD if (slotValType == ValType::V128) { return iter().fail("Ion has no SIMD support yet"); } @@ -667,7 +667,7 @@ class FunctionCompiler { // Initialize all local slots to zero value for (size_t i = type.args().length(); i < locals_.length(); i++) { ValType slotValType = locals_[i]; -#ifndef ENABLE_JIT_SIMD +#ifndef ENABLE_WASM_SIMD if (slotValType == ValType::V128) { return iter().fail("Ion has no SIMD support yet"); } @@ -777,7 +777,7 @@ class FunctionCompiler { template MDefinition* constantTargetWord(T) = delete; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* constantV128(V128 v) { if (inDeadCode()) { return nullptr; @@ -808,7 +808,7 @@ class FunctionCompiler { return constantI32(0); case ValType::I64: return constantI64(int64_t(0)); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: return constantV128(V128(0)); #endif @@ -1294,7 +1294,7 @@ class FunctionCompiler { return ins; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // About Wasm SIMD as supported by Ion: // // The expectation is that Ion will only ever support SIMD on x86 and x64, @@ -1434,7 +1434,7 @@ class FunctionCompiler { // Also see below for SIMD memory references -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD /************************************************ Linear memory accesses */ @@ -1927,7 +1927,7 @@ class FunctionCompiler { return binop; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* loadSplatSimd128(Scalar::Type viewType, const LinearMemoryAddress& addr, wasm::SimdOp splatOp) { @@ -2041,7 +2041,7 @@ class FunctionCompiler { } curBlock_->add(store); } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD /************************************************ Global variable accesses */ @@ -2546,7 +2546,7 @@ class FunctionCompiler { } break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: MOZ_CRASH("SIMD128 not supported in builtin ABI"); #endif @@ -2622,7 +2622,7 @@ class FunctionCompiler { result.type().toMaybeRefType()); break; case wasm::ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD def = MWasmFloatRegisterResult::New(alloc(), MIRType::Simd128, result.fpr()); #else @@ -6790,7 +6790,7 @@ bool FunctionCompiler::emitGetGlobal() { result = constantF64(value.f64()); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD result = constantV128(value.v128()); break; #else @@ -7594,7 +7594,7 @@ bool FunctionCompiler::emitMemCopyInline(uint32_t memoryIndex, MDefinition* dst, // Compute the number of copies of each width we will need to do size_t remainder = length; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD size_t numCopies16 = 0; if (MacroAssembler::SupportsFastUnalignedFPAccesses()) { numCopies16 = remainder / sizeof(V128); @@ -7617,7 +7617,7 @@ bool FunctionCompiler::emitMemCopyInline(uint32_t memoryIndex, MDefinition* dst, size_t offset = 0; DefVector loadedValues; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { MemoryAccessDesc access(memoryIndex, Scalar::Simd128, 1, offset, trapSiteDesc(), hugeMemoryEnabled(memoryIndex)); @@ -7717,7 +7717,7 @@ bool FunctionCompiler::emitMemCopyInline(uint32_t memoryIndex, MDefinition* dst, } #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { offset -= sizeof(V128); @@ -7842,7 +7842,7 @@ bool FunctionCompiler::emitMemFillInline(uint32_t memoryIndex, // Compute the number of copies of each width we will need to do size_t remainder = length; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD size_t numCopies16 = 0; if (MacroAssembler::SupportsFastUnalignedFPAccesses()) { numCopies16 = remainder / sizeof(V128); @@ -7860,7 +7860,7 @@ bool FunctionCompiler::emitMemFillInline(uint32_t memoryIndex, size_t numCopies1 = remainder; // Generate splatted definitions for wider fills as needed -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD MDefinition* val16 = numCopies16 ? constantV128(V128(value)) : nullptr; #endif #ifdef JS_64BIT @@ -7914,7 +7914,7 @@ bool FunctionCompiler::emitMemFillInline(uint32_t memoryIndex, } #endif -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD for (uint32_t i = 0; i < numCopies16; i++) { offset -= sizeof(V128); @@ -8469,7 +8469,7 @@ bool FunctionCompiler::emitI64MulWide(bool isSigned) { // // SIMD support -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD bool FunctionCompiler::emitConstSimd128() { V128 v128; if (!iter().readV128Const(&v128)) { @@ -8653,7 +8653,7 @@ bool FunctionCompiler::emitStoreLaneSimd128(uint32_t laneSize) { return true; } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD bool FunctionCompiler::emitRefAsNonNull() { MDefinition* ref; @@ -10604,7 +10604,7 @@ bool FunctionCompiler::emitBodyExprs() { } // SIMD operations -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case uint16_t(Op::SimdPrefix): { if (!codeMeta().simdAvailable()) { return iter().unrecognizedOpcode(&op); diff --git a/js/src/wasm/WasmOpIter.cpp b/js/src/wasm/WasmOpIter.cpp index 28c996164091..8a95206513ef 100644 --- a/js/src/wasm/WasmOpIter.cpp +++ b/js/src/wasm/WasmOpIter.cpp @@ -22,7 +22,7 @@ using namespace js; using namespace js::jit; using namespace js::wasm; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD # define WASM_SIMD_OP(code) return code #else # define WASM_SIMD_OP(code) break diff --git a/js/src/wasm/WasmOpIter.h b/js/src/wasm/WasmOpIter.h index 7235630c8be2..eef543665ddc 100644 --- a/js/src/wasm/WasmOpIter.h +++ b/js/src/wasm/WasmOpIter.h @@ -107,7 +107,7 @@ class StackType { case ValType::F32: case ValType::I64: case ValType::F64: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: #endif return true; @@ -217,7 +217,7 @@ enum class OpKind { RefCast, BrOnCast, RefConversion, -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD ExtractLane, ReplaceLane, LoadLane, @@ -843,7 +843,7 @@ class MOZ_STACK_CLASS OpIter : private Policy { [[nodiscard]] bool readRefConversion(RefType operandType, RefType resultType, Value* operandValue); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD [[nodiscard]] bool readLaneIndex(uint32_t inputLanes, uint32_t* laneIndex); [[nodiscard]] bool readExtractLane(ValType resultType, uint32_t inputLanes, uint32_t* laneIndex, Value* input); @@ -4273,7 +4273,7 @@ inline bool OpIter::readRefConversion(RefType operandType, return true; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD template inline bool OpIter::readLaneIndex(uint32_t inputLanes, @@ -4462,7 +4462,7 @@ inline bool OpIter::readStoreLane(uint32_t byteSize, return true; } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD #ifdef ENABLE_WASM_JSPI diff --git a/js/src/wasm/WasmStubs.cpp b/js/src/wasm/WasmStubs.cpp index d96ba8348622..8a98e201a452 100644 --- a/js/src/wasm/WasmStubs.cpp +++ b/js/src/wasm/WasmStubs.cpp @@ -59,7 +59,7 @@ static uint32_t ResultStackSize(ValType type) { return ABIResult::StackSizeOfFloat; case ValType::F64: return ABIResult::StackSizeOfDouble; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: return ABIResult::StackSizeOfV128; #endif @@ -85,7 +85,7 @@ uint32_t js::wasm::MIRTypeToABIResultSize(jit::MIRType type) { return ABIResult::StackSizeOfFloat; case MIRType::Double: return ABIResult::StackSizeOfDouble; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case MIRType::Simd128: return ABIResult::StackSizeOfV128; #endif @@ -121,7 +121,7 @@ void ABIResultIter::settleRegister(ValType type) { case ValType::Ref: cur_ = ABIResult(type, ReturnReg); break; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case ValType::V128: cur_ = ABIResult(type, ReturnSimd128Reg); break; @@ -302,7 +302,7 @@ static void GenPrintF64(DebugChannel channel, MacroAssembler& masm, }); } -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD static void GenPrintV128(DebugChannel channel, MacroAssembler& masm, const FloatRegister& src) { // TODO: We might try to do something meaningful here once SIMD data are @@ -323,7 +323,7 @@ static void GenPrintF32(DebugChannel channel, MacroAssembler& masm, const FloatRegister& src) {} static void GenPrintF64(DebugChannel channel, MacroAssembler& masm, const FloatRegister& src) {} -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD static void GenPrintV128(DebugChannel channel, MacroAssembler& masm, const FloatRegister& src) {} # endif @@ -409,7 +409,7 @@ static void SetupABIArguments(MacroAssembler& masm, const FuncExport& fe, masm.loadFloat32(src, iter->fpu()); break; case MIRType::Simd128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // This is only used by the testing invoke path, // wasmLosslessInvoke, and is guarded against in normal JS-API // call paths. @@ -456,7 +456,7 @@ static void SetupABIArguments(MacroAssembler& masm, const FuncExport& fe, break; } case MIRType::Simd128: { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD // This is only used by the testing invoke path, // wasmLosslessInvoke, and is guarded against in normal JS-API // call paths. @@ -504,7 +504,7 @@ static void StoreRegisterResult(MacroAssembler& masm, const FuncExport& fe, masm.store64(result.gpr64(), Address(loc, 0)); break; case ValType::V128: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD masm.storeUnalignedSimd128(result.fpr(), Address(loc, 0)); break; #else @@ -1642,7 +1642,7 @@ static void StackCopy(MacroAssembler& masm, MIRType type, Register scratch, masm.loadDouble(src, fpscratch); GenPrintF64(DebugChannel::Import, masm, fpscratch); masm.storeDouble(fpscratch, dst); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD } else if (type == MIRType::Simd128) { ScratchSimd128Scope fpscratch(masm); masm.loadUnalignedSimd128(src, fpscratch); @@ -2623,7 +2623,7 @@ static const LiveRegisterSet RegsToPreserve( ~((Registers::SetType(1) << Registers::sp) | (Registers::SetType(1) << Registers::pc))), FloatRegisterSet(FloatRegisters::AllDoubleMask)); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD # error "high lanes of SIMD registers need to be saved too." # endif #elif defined(JS_CODEGEN_MIPS64) @@ -2634,7 +2634,7 @@ static const LiveRegisterSet RegsToPreserve( (Registers::SetType(1) << Registers::sp) | (Registers::SetType(1) << Registers::zero))), FloatRegisterSet(FloatRegisters::AllDoubleMask)); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD # error "high lanes of SIMD registers need to be saved too." # endif #elif defined(JS_CODEGEN_LOONG64) @@ -2645,7 +2645,7 @@ static const LiveRegisterSet RegsToPreserve( (uint32_t(1) << Registers::sp) | (uint32_t(1) << Registers::zero))), FloatRegisterSet(FloatRegisters::AllDoubleMask)); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD # error "high lanes of SIMD registers need to be saved too." # endif #elif defined(JS_CODEGEN_RISCV64) @@ -2656,7 +2656,7 @@ static const LiveRegisterSet RegsToPreserve( (uint32_t(1) << Registers::sp) | (uint32_t(1) << Registers::zero))), FloatRegisterSet(FloatRegisters::AllDoubleMask)); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD # error "high lanes of SIMD registers need to be saved too." # endif #elif defined(JS_CODEGEN_ARM64) @@ -2667,7 +2667,7 @@ static const LiveRegisterSet RegsToPreserve( GeneralRegisterSet(Registers::AllMask & ~((Registers::SetType(1) << RealStackPointer.code()) | (Registers::SetType(1) << Registers::lr))), -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD FloatRegisterSet(FloatRegisters::AllSimd128Mask)); # else // If SIMD is not enabled, it's pointless to save/restore the upper 64 @@ -2685,7 +2685,7 @@ static const LiveRegisterSet RegsToPreserve( #else static const LiveRegisterSet RegsToPreserve( GeneralRegisterSet(0), FloatRegisterSet(FloatRegisters::AllDoubleMask)); -# ifdef ENABLE_JIT_SIMD +# ifdef ENABLE_WASM_SIMD # error "no SIMD support" # endif #endif diff --git a/js/src/wasm/WasmStubs.h b/js/src/wasm/WasmStubs.h index 0af2b61954cf..d18eca7031d2 100644 --- a/js/src/wasm/WasmStubs.h +++ b/js/src/wasm/WasmStubs.h @@ -85,7 +85,7 @@ class ABIResult { static constexpr size_t StackSizeOfFloat = sizeof(double); #endif static constexpr size_t StackSizeOfDouble = sizeof(double); -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD static constexpr size_t StackSizeOfV128 = sizeof(V128); #endif diff --git a/js/src/wasm/WasmValType.cpp b/js/src/wasm/WasmValType.cpp index d2a76700e684..a83bf7ff6ce7 100644 --- a/js/src/wasm/WasmValType.cpp +++ b/js/src/wasm/WasmValType.cpp @@ -294,7 +294,7 @@ bool wasm::ToValType(JSContext* cx, HandleValue v, ValType* out) { *out = ValType::F32; } else if (StringEqualsLiteral(typeLinearStr, "f64")) { *out = ValType::F64; -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD } else if (SimdAvailable(cx) && StringEqualsLiteral(typeLinearStr, "v128")) { *out = ValType::V128; #endif diff --git a/js/src/wasm/WasmValType.h b/js/src/wasm/WasmValType.h index 93f02670df25..3a17a3034887 100644 --- a/js/src/wasm/WasmValType.h +++ b/js/src/wasm/WasmValType.h @@ -539,7 +539,7 @@ class StorageTypeTraits { case TypeCode::I64: case TypeCode::F32: case TypeCode::F64: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case TypeCode::V128: #endif case TypeCode::FuncRef: @@ -589,7 +589,7 @@ class StorageTypeTraits { static bool isVectorTypeCode(TypeCode tc) { switch (tc) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case TypeCode::V128: return true; #endif @@ -634,7 +634,7 @@ class ValTypeTraits { case TypeCode::I64: case TypeCode::F32: case TypeCode::F64: -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case TypeCode::V128: #endif case TypeCode::FuncRef: @@ -676,7 +676,7 @@ class ValTypeTraits { static bool isVectorTypeCode(TypeCode tc) { switch (tc) { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case TypeCode::V128: return true; #endif @@ -851,7 +851,7 @@ class PackedType : public T { // Returns whether the type has a representation in JS. bool isExposable() const { -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD if (kind() == Kind::V128) { return false; } diff --git a/js/src/wasm/WasmValidate.cpp b/js/src/wasm/WasmValidate.cpp index 5676fd759070..04fb987d00ca 100644 --- a/js/src/wasm/WasmValidate.cpp +++ b/js/src/wasm/WasmValidate.cpp @@ -1296,7 +1296,7 @@ bool wasm::ValidateOps(ValidatingOpIter& iter, T& dumper, break; } -#ifdef ENABLE_JIT_SIMD +#ifdef ENABLE_WASM_SIMD case uint16_t(Op::SimdPrefix): { if (!codeMeta.simdAvailable()) { return iter.unrecognizedOpcode(&op); @@ -1908,7 +1908,7 @@ bool wasm::ValidateOps(ValidatingOpIter& iter, T& dumper, } break; } -#endif // ENABLE_JIT_SIMD +#endif // ENABLE_WASM_SIMD case uint16_t(Op::MiscPrefix): { switch (op.b1) { diff --git a/js/xpconnect/src/nsXPConnect.cpp b/js/xpconnect/src/nsXPConnect.cpp index c9c5165ebb6a..fc50c3260009 100644 --- a/js/xpconnect/src/nsXPConnect.cpp +++ b/js/xpconnect/src/nsXPConnect.cpp @@ -97,7 +97,7 @@ static bool IsLockdownModeEnabled() { #endif static void InitJSEngine() { -#if defined(ENABLE_JIT_SIMD) && \ +#if defined(ENABLE_WASM_SIMD) && \ (defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86)) // Update static engine preferences, such as AVX, before // `JS_InitWithFailureDiagnostic` is called. diff --git a/modules/libpref/init/StaticPrefList.yaml b/modules/libpref/init/StaticPrefList.yaml index 928a2879c003..557044b80c1d 100644 --- a/modules/libpref/init/StaticPrefList.yaml +++ b/modules/libpref/init/StaticPrefList.yaml @@ -9705,7 +9705,7 @@ mirror: always set_spidermonkey_pref: always -#if defined(ENABLE_JIT_SIMD) +#if defined(ENABLE_WASM_SIMD) #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) # Enables AVX instructions support on X86/X64 platforms. # Changing these prefs requires a restart.